3D Ferroelectric Memory Staircase Layout for Multi-Level Programming
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Solution Overview
Problem
Existing 3D memory devices, such as 3D vertical stacked ferroelectric structures, face challenges in achieving high-density, low-power operation and efficient multi-level programming for advanced applications like AI operations, particularly in Deep Neural Networks (DNN) and Convolutional Neural Networks (CNN), due to limitations in scalability and complexity.
Innovation Solution
A 3D vertical memory device with a multi-layer stack forming a staircase structure, where memory cells are stacked vertically and shared word lines connect pairs of memory cells, allowing for different on-current levels, enabling multi-level programming and enhanced storage capacity and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D vertical stacked ferroelectric structures are used, then storage density is improved, but device complexity increases
Solution Approach 1:
The memory device is divided into multiple stacked memory cell layers, with each layer containing memory cells formed between word lines and bit lines. This segmentation allows the storage capacity to be increased vertically rather than horizontally, improving storage density while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to 3D vertical stacked architecture. Memory cells are arranged in multiple layers stacked vertically, with word lines extending in first directions and bit lines in second directions perpendicular to the word lines. This dimensional change enables significantly higher storage density without proportionally increasing device complexity.
2Quantity of substance
If multi-level programming is implemented, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements multi-level programming by controlling the resistance state of memory cells through precise control of programming currents. By applying different current magnitudes and durations, multiple resistance levels can be achieved, enabling multi-bit storage per cell. This parameter-based approach increases storage capacity without requiring additional physical layers or structures.
Solution Approach 2:
The same memory cell structure and materials are used for both binary and multi-level programming operations. The ferroelectric field-effect transistor-based memory cells can operate in different modes (binary or multi-level) depending on the programming scheme applied, providing versatility without increasing manufacturing complexity.
3Quantity of substance
If vertically stacked memory cells are used, then storage density is improved, but power consumption increases
Solution Approach 1:
The patent merges the word line and gate electrode functions into a single structure. The word lines serve dual purposes as both bit line connections and gate electrodes for controlling the ferroelectric field-effect transistors. This merging reduces the number of separate conductive layers and connections required, thereby reducing overall power consumption while maintaining high storage density through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves increased storage density and power efficiency by allowing multi-level programming, making it suitable for AI applications like DNN and CNN computations through its unique cell configuration and ferroelectric material-based operation.
Implementation Method 1
a gate dielectric layer including a ferroelectric material
Data Source
AI summary
Provided are a memory device and a method of forming the same. The memory device includes a substrate, a multi-layer stack, a plurality of memory cells, and a plurality of conductive contacts. The substrate includes an array region and a staircase region. The multi-layer stack is disposed on the substrate in the array region, wherein the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure. The plurality of memory cells are respectively disposed on sidewalls of the multi-layer stack in the array region, and arranged at least along a stacking direction of the multi-layer stack. The plurality of conductive contacts are respectively on the staircase structure. At least two conductive contacts are electrically connected to each other.