Digital Storage TRIZ Cases

A symmetrical H-shaped bit line selector keeps DRAM bit lines straighter to cut voltage drop, delay, coupling noise, and alignment difficulty.

Vertically stacked ferroelectric cells use shared word lines and a staircase contact layout to raise density while enabling low-power multi-level programming.

Selective low- and high-power drivers raise internal voltage quickly while keeping bit-line levels stable to prevent overcharging during sensing.

A higher bitline voltage with lower-voltage logic cuts DRAM switching power while preserving signal swing where the memory array needs it.

By distributing signal development transistors across memory die levels, this case cuts routing area, shortens access lines, and supports higher density.

A shaped resistive layer and threshold-switching selector lower hold current without thicker films, reducing oscillation and memory cell failures.

Local select-switch biasing limits current surges when threshold selector switches turn on, protecting MRAM cells and preserving data.

Grouped PMOS and NMOS decoder switches cut cross-point MRAM routing area while preserving bipolar bit-line and word-line operation.

A buffer die inside the memory package splits Reed-Solomon error correction across memory dies to improve communication and reliability.

Selective word-line refresh cuts self-refresh power use and shortens the delay from exit self-refresh to valid memory commands.

A buffer die detects command conflicts with memory housekeeping and queues traffic to preserve deterministic timing and data integrity.

Delayed word line assertion after bit lines pull low cuts storage-node contention, reducing write power, failures, and delay.

Separate signal routing and local processing keep control-signal delay mismatch below a threshold while saving memory wiring space.

PRAC cells track row activation so DRAM refresh targets only activated word lines, reducing standby power without losing data retention.

Shared pull-down transistors adjust adjacent SRAM word-line voltages to improve read SNM while cutting WL driver area and loading.

Combining internal and external memory cuts communication delay while expanding usable capacity for faster data processing.

A buffer die inside the memory package handles multiplexing and buffering to cut module components, reduce latency, and improve bandwidth.

Voltage-to-time readout and current-source SRAM cells improve low-voltage MAC accuracy, throughput, and energy efficiency.

Active-count and error-history tracking selects vulnerable rows for refresh, reducing row hammer errors while limiting bandwidth loss.

Point-to-point links and dual data interfaces let RDIMMs add more modules and ranks without degrading signaling integrity at top data rates.

A buffer die inside the memory package reallocates ECC storage by device error rate, improving data integrity without fixed ECC overhead.

High- and low-entropy data are placed in different memory devices by temperature state to cut power use and reduce thermal stress.

Variable gate control calibrates PMOS and NMOS driver impedance across multiple memory voltages, cutting area, stress, and calibration time.

Multiple local TSVs and daisy-chained buffers distribute clock signals across tall memory stacks while limiting parasitic loading and retuning timing.

Compensation voltages on MRAM source and bit lines cut IR drop, lower write voltage demand, and widen low-temperature write margin.

A diffusion barrier between two oxide dielectric layers blocks oxygen vacancy migration, stabilizing OxRAM states and widening read margins.

Voltage-threshold switching and a shared read/write path improve MTJ resistance-state detection for more accurate and reliable data storage.

An added die stores redundant data outside the main array, enabling dynamic remapping of defective cells while improving yield and storage use.

Varying global interconnect lengths and switch circuits balance cell resistance in large memory arrays, improving stability and access efficiency.

Selective power gating splits DRAM row decoder driver groups to cut standby leakage while preserving reliable memory operation.

Extra RRAM states encode hidden chip ID data that reads normally in standard mode but becomes detectable under controlled non-regular conditions.

A Ge-As-Se-O memory layer combines selector and storage functions to suppress sneak current while improving stability and threshold-voltage drift.

Dual-layer insulation and encapsulation improve heat retention and uniform heating in phase-change memory cells, cutting write energy.

Asymmetrical dual-read access circuits shrink SRAM bit-cell area and capacitive loading while preserving floor-planning and read performance.

A two-part MTJ free layer uses local metal doping to speed switching while preserving tunneling magnetoresistance and data retention.

Maintaining both row and column ECC with caching cuts write amplification in column-addressable memory and preserves dynamic-data performance.

Interleaving PASR requests across asymmetrical DRAM ranks cuts refresh power use while improving balanced parallel memory refresh.

Variable gate voltages and pull-up/pull-down stop signals let one memory interface driver calibrate impedance across voltage domains with less area.

Permanent-state fault marking enables LUT-free bitwise memory repair, cutting latency and power while preserving memory density.

Stacked MTJ sets in a 3T4M MRAM cell enable multistate read and write while increasing memory capacity within limited layout area.

A polarized magnetic layer built into the MTJ selector tilts the free layer, cutting incubation time while keeping the memory cell compact.

Inverted bit-line and source-line biasing cuts MRAM leakage and improves Ion/Ioff, enabling reliable low-power cell state sensing.

A single ambipolar FET with threshold modulation replaces dual CAM paths, reducing cell area, search latency, and power.

Integrated hybrid storage blocks place data and OD-ECC together to cut layout area, shorten response time, and preserve data integrity.

Switches, resistor strings, and multiplexers tune reference voltage levels for different DDR SDRAMs to improve data interpretation accuracy.

Hierarchical high- and low-address frequency counting identifies row hammer refresh addresses accurately with simpler circuitry and less chip area.

Stacked memory layers use aligned openings to route word lines to control circuits, boosting density while simplifying wiring and fabrication.

Diagonal-sidewall cell pads formed by double patterning improve bit line contact alignment, cut resistance, and keep pad areas consistent.

A middle circuit chip uses front and backside interconnects to expand bond pads, raise memory density, and shorten read/write paths.

A stacked CFET header switch uses a diode-connected transistor pair to improve resistance ratio and shrink chip area in memory power delivery.