Current-Domain In-Memory SRAM MAC With Voltage-to-Time Readout

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Solution Overview

Problem

Conventional in-memory compute SRAMs face limitations in computing accuracy, throughput, and energy efficiency due to non-linearities, process variations, and limited signal margins, especially at low voltage operations.

Innovation Solution

A 12T-SRAM design with a current-source transistor in the read-port, coupled to a voltage-to-time conversion block, enables a current-controlled structure that overcomes these limitations by providing linear, energy-efficient, and reconfigurable subthreshold MAC operations, with features like negative feedback and current sensing to adjust MAC speed and throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional in-memory compute SRAMs are used, then MAC operations can be performed in-place, but computing accuracy deteriorates due to non-linearities and process variations

Engineering Contradiction:

Improvecomputing accuracyVSAvoidsignal margin

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent introduces a voltage-to-time conversion block as an intermediary between the voltage domain input signals and the current domain MAC operations. This conversion block transforms voltage inputs into time-domain signals that control the duration of current flow through the SRAM cells, thereby linearizing the MAC operation and reducing the impact of process variations and non-linearities while maintaining signal margins

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the operational domain from direct voltage-domain operations to time-domain controlled current operations. By converting the input voltage signals to time-domain pulse widths and using these to control current flow duration, the system achieves linear MAC operations with improved accuracy and reduced sensitivity to process variations

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If conventional in-memory compute SRAMs are used, then data movement is reduced, but energy efficiency deteriorates due to excessive power consumption

Engineering Contradiction:

Improveenergy efficiencyVSAvoidpower consumption

Core Design Contradiction:

Use of energy by moving objectVSLoss of energy

Solution Approach 1:

The patent employs periodic pulsed current operations where current flows through the SRAM cells only during specific time windows determined by the voltage-to-time conversion. This periodic action allows the system to perform MAC operations with controlled energy expenditure, reducing overall power consumption while maintaining computational functionality

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent transitions from continuous voltage-domain operations to discrete time-domain pulsed operations. By controlling the duration and timing of current flow based on converted time signals, the system achieves superior energy efficiency with measured values of 580 TOPS/W for 1 kbit and 2128 TOPS/W for 16 kbit SRAM configurations

Inventive Principle:

Principle #35Parameter changes

3Productivity

If conventional in-memory compute SRAMs are used, then parallelism is achieved, but throughput deteriorates due to limited signal margins

Engineering Contradiction:

ImprovethroughputVSAvoidsignal margin

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The voltage-to-time conversion block serves as a mediator that transforms voltage signals into time-domain control signals, enabling parallel MAC operations across multiple SRAM rows with improved signal margins. This conversion ensures that each parallel operation has sufficient time-window separation and signal integrity, thereby increasing overall throughput

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design achieves high energy efficiency (580 TOPS/W for 1 kbit and 2128 TOPS/W for 16 kbit), improved MAC accuracy, and reduced process variations, eliminating the need for ADCs/DACs between neural network layers, while supporting different precisions and speeds.

Implementation Method 1

A read-port is coupled to a voltage-to-time (VTC) conversion block

Methodology Applied

Scientific EffectVoltage-to-time conversion:

Implementation Method 2

Analog MAC computing is performed by accumulating the SRAM cells' bitline discharging currents resulting from multiplying inputs by stored weights

Methodology Applied

Scientific EffectElectrical conduction and current multiplication: Conduction (electrical)

Implementation Method 3

A current sense amplifier coupled to a read bit line on an output of the read-port

Methodology Applied

Scientific EffectElectrical resistance sensing: Electrical Resistance

Data Source

PatentUS20260065981A1Reconfigurable analog current-domain in-memory compute SRAM design for low-power applications

Publication Date: 2026.03.05 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A static random-access memory (SRAM) device a read-port coupled to a voltage-to-time (VTC) conversion block. The read-port comprises a first transistor coupled to a pair of cross-coupled inverters. A pass gate transistor is coupled to the first transistor. A current-source transistor is coupled to the pass gate transistor. A row of the SRAM device is configured to generate a read wordline signal multiplied by one or more SRAM stored weights in response to receiving a voltage vector. The row is further configured to generate analog outputs for a multiply and compute operation (MAC).