Memory Refresh Target Selection for Row Hammer Protection
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Solution Overview
Problem
Volatile memories like DRAM suffer from the row hammering phenomenon, where data loss occurs due to excessive activations of specific rows, necessitating additional target refresh operations to prevent damage to these rows and their neighboring cells.
Innovation Solution
A memory system with a refresh target selection circuit that selects target rows for refresh based on active operation counts and error histories, incorporating an access count cell region to store these metrics and an error correction mechanism to correct and log errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If target refresh operation is performed on rows with high active operation counts to prevent row hammering, then data integrity is improved, but memory bandwidth and performance are reduced due to additional refresh operations
Solution Approach 1:
The patent performs target refresh operations proactively on rows that are likely to be affected by row hammering, based on monitored active operation counts and error histories, before actual data corruption occurs. This preliminary action prevents data integrity issues while allowing the memory system to maintain normal operation during non-refresh periods.
Solution Approach 2:
The patent implements a feedback mechanism that monitors active operation counts for each row and maintains error histories, using this information to dynamically determine which rows require target refresh operations. This feedback-driven approach ensures refresh operations are performed only when necessary, optimizing the balance between data integrity and memory bandwidth utilization.
2Reliability
If active operation counts are monitored for each row to identify target refresh candidates, then row hammering prevention is improved, but device complexity increases due to additional monitoring and storage requirements
Solution Approach 1:
The access count cell region serves multiple functions: it stores active operation counts for row hammering detection, provides error history information for refresh target selection, and enables performance analysis. This multi-functionality reduces the need for separate dedicated circuits for each monitoring task, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent combines the monitoring of active operation counts and the storage of error histories into a unified access count cell region that works integrated with the existing refresh control logic. This merging approach allows the system to gain enhanced row hammering prevention capabilities while minimizing additional circuit complexity by reusing existing memory structures and control pathways.
Data Source
AI summary
A memory may include a cell array including memory cells arranged in a plurality of rows and a plurality of columns, and a refresh target selection circuit configured to select a target row for a target refresh operation based on a quantity of active operations for each row in the cell array and an error history for each row.