Multi-Level Signal Development Layouts for Dense Memory Dies
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Solution Overview
Problem
Memory devices face scaling limitations due to the increasing area required for signal development circuitry as the number of memory levels increases, leading to reduced density and scalability.
Innovation Solution
Positioning signal development circuitry in multiple levels of a memory die relative to a substrate, with sets of transistors on different levels, leveraging common manufacturing processes to enhance memory cell density and access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If signal development circuitry is positioned in a single level, then the structure is simple, but the area occupied increases and density decreases
Solution Approach 1:
The patent applies dimensionality change by transitioning from a single-level planar arrangement to a multi-level three-dimensional configuration. Signal development circuitry is distributed across multiple levels (first level, second level, third level) above the substrate, utilizing the vertical dimension to reduce the horizontal area occupied by the circuitry while maintaining functional integrity.
2Speed
If signal development circuitry is positioned closer to memory cells, then access operations are improved, but the area required for routing increases
Solution Approach 1:
The patent utilizes vertical stacking to position signal development circuitry at multiple levels in close proximity to memory cells. This three-dimensional arrangement shortens access line lengths and improves signal development speed while efficiently utilizing the vertical space to minimize the horizontal routing area.
Solution Approach 2:
The patent implements a nested arrangement where signal development circuitry at different levels is vertically stacked and positioned over different regions of the substrate. This nesting approach allows multiple circuit components to occupy overlapping horizontal footprints at different vertical levels, reducing the total area required for routing and access lines.
3Quantity of substance
If the number of memory levels increases, then memory density increases, but the area required for signal development circuitry increases
Solution Approach 1:
The patent addresses the scaling challenge by distributing signal development circuitry across multiple vertical levels. As the number of memory levels increases, the circuitry is similarly distributed in the vertical dimension, allowing memory density to increase without proportionally increasing the horizontal area occupied by signal development circuitry.
Data Source
AI summary
Methods, systems, and devices for signal development circuitry layouts in a memory device are described. A memory device may include signal development circuitry that is positioned in multiple levels of a memory die relative to a substrate. For example, a set of first transistors used for developing access signals may be located on a first level of a memory die, and a set of second transistors used for developing the access signals may be located on a second level of the memory die. Formation of the set of first transistors and the set of second transistors may involve processing operations that are common with the formation of other transistors on a respective level, such as cell selection transistors, deck selection transistors, shunting transistors, and other transistors of the respective level.