Dual-Read SRAM Bit Cell Layout With Asymmetrical Read Access
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Solution Overview
Problem
The dimensions of static random access memory (SRAM) components often exceed the limits for efficient placement on a semiconductor chip, interfering with the placement of other components and rendering the chip inoperable without significant redesign.
Innovation Solution
The use of asymmetrical read access circuits with dual read ports in memory bit cells, which include more p-type or n-type transistors than n-type or p-type transistors respectively, reduces on-die area and capacitive loading, allowing for efficient floor planning and reduced transistor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional symmetrical read access circuits are used in memory bit cells, then the circuit provides balanced read access capability, but the on-die area occupied by each bit cell increases and capacitive loading increases
Solution Approach 1:
The patent applies asymmetry by designing read access circuits with unequal numbers of p-type and n-type transistors. Specifically, one read port uses a circuit with more p-type transistors while the other read port uses a circuit with more n-type transistors. This asymmetric design reduces the total transistor count per bit cell compared to symmetrical designs, thereby reducing on-die area and capacitive loading while maintaining dual read port functionality.
2Adaptability or versatility
If dual read ports are implemented in memory bit cells, then the memory provides increased read access versatility, but the transistor count and circuit complexity increase
Solution Approach 1:
The patent reduces circuit complexity by using asymmetrical read access circuits where each read port has a different transistor composition (one with more p-type transistors, the other with more n-type transistors). This asymmetric approach achieves dual read port versatility while minimizing the total transistor count compared to conventional symmetrical dual read port designs.
Solution Approach 2:
The asymmetrical read access circuit design provides universal read access capability across both read ports. The circuits are designed to handle read operations efficiently regardless of which port is accessed, achieving multi-functionality with reduced complexity by leveraging the complementary strengths of p-type and n-type transistor configurations.
3Area of stationary object
If memory bit cells use asymmetrical read access circuits, then the on-die area is reduced and floor planning is improved, but the circuit design becomes more complex
Solution Approach 1:
The patent achieves area reduction through asymmetrical circuit design where each read port uses a different transistor configuration. This asymmetric approach minimizes the total transistor count per bit cell, directly reducing on-die area and improving floor planning efficiency.
Solution Approach 2:
The patent applies local quality by optimizing each read port's circuit configuration based on its specific requirements. One read port uses a configuration with more p-type transistors while the other uses more n-type transistors, allowing each local circuit to be optimized for its function while contributing to overall area reduction.
Data Source
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AI summary
An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.