MRAM Cell Layout With Stacked MTJs for Higher Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of miniaturizing memory cells and increasing memory capacity within a limited layout area in MRAM technology has hindered its widespread application in semiconductor chips.
Innovation Solution
A novel MRAM circuit and layout featuring multiple stacked magnetic tunnel junctions (MTJs) in series connection, integrated with a 3T4M architecture, allowing for multistate write and read operations, and optimized layout structure to enhance memory capacity in unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MRAM memory cell layout is used, then device simplicity is maintained, but memory capacity per unit layout area is limited
Solution Approach 1:
The patent implements vertically stacked MTJs in series connection, transitioning from a planar two-dimensional layout to a three-dimensional vertical structure. Multiple MTJs (at least two) are stacked along the vertical direction within the same footprint area, effectively increasing memory capacity without expanding the horizontal layout area.
Solution Approach 2:
The patent embeds multiple MTJs within each other in a vertical stack configuration, where MTJs are nested along the vertical axis. This nesting approach allows multiple storage elements to occupy the same horizontal space by utilizing the vertical dimension, thereby increasing density.
2Quantity of substance
If more memory cells are accommodated in limited layout area, then memory capacity increases, but device complexity increases
Solution Approach 1:
The patent employs a 3T4M architecture where three transistors control four MTJs (organized as two MTJ sets with at least two MTJs each in series). This multi-functional design allows the same transistor and interconnect structures to serve multiple storage nodes, increasing memory capacity while managing device complexity through shared control mechanisms.
Solution Approach 2:
The patent merges multiple MTJs into series-connected sets, where at least two MTJs are combined in each set. This merging approach allows multiple storage elements to be controlled through shared transistor gates and interconnect lines, increasing capacity while reducing the number of independent control circuits needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased memory capacity and improved layout utilization by implementing multistate operations, enhancing the potential of MRAM for broader applications in memory technology.
Implementation Method 1
an external magnetic field is applied in the write operation of MRAM to control the polarization direction of MTJs and obtain different tunnel magnetoresistances (TMR)
Implementation Method 2
obtain different tunnel magnetoresistances (TMR)
Data Source
AI summary
A MRAM circuit is provided in the present invention, wherein each memory cell has three transistors, including a first transistor, a third transistor and a second transistor connected in order and series connection, a first node is connected between the first transistor and the third transistor, a second node is connected between the second transistor and the third transistor, and a common source line is connected with one terminal of the first transistor and the second transistor. A first MTJ set includes at least two MTJs in series connection and with one terminal connected to the first node, and a second MTJ set includes at least two MTJs in series connection and with one terminal connected to the second node.