Bipolar MRAM Decoder Layout for Reduced Routing Area
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Solution Overview
Problem
The complex routing of bipolar decoders in nonvolatile memory arrays, particularly in cross-point architectures, consumes significant area on the memory die, necessitating a reduction in layout space and improving the efficiency of decoding structures.
Innovation Solution
The decoders are split into sub-sets with inverters aligned on the die to share bit line and word line enable signals, reducing the area required for decoding and optimizing the layout by separating bipolar select switches into distinct groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bipolar decoders are used in cross-point memory arrays, then memory operations can be performed effectively, but the routing consumes significant area on the memory die
Solution Approach 1:
The decoder routing is segmented into separate paths: a first set of routing for first-story memory cells and a second set of routing for second-story memory cells. This segmentation allows each routing path to be optimized independently, reducing the total area required for decoder routing while maintaining effective memory operations for both stories
Solution Approach 2:
The patent utilizes vertical stacking of memory stories in the third dimension, allowing multiple memory layers to be accessed through separate routing paths that extend in different spatial dimensions. This dimensional approach reduces the planar area required for routing by utilizing vertical space and multi-layer interconnect structures
2Adaptability or versatility
If complex routing is used to access memory cells in multiple stories, then all memory cells can be accessed, but the layout space is reduced
Solution Approach 1:
The memory array is segmented into multiple stories with dedicated routing paths for each story. First-story memory cells are accessed through a first set of routing, while second-story memory cells are accessed through a second set of routing. This segmentation enables comprehensive memory cell accessibility while reducing layout space by avoiding the need for a single complex universal routing structure
Solution Approach 2:
The decoder structure is designed with multi-functional routing paths that can serve different memory stories. The routing architecture enables a single decoder to control access to multiple stories through separate, optimized paths, providing universal access capability without requiring proportionally increased layout space
Data Source
AI summary
To program MRAM memory cells current must flow from the memory cell's corresponding bit line to its corresponding word line or from the word line to bit line. To accomplish this, the bit line and word line decoders must be capable of sourcing current (when driving a line positive) and sinking current (when pulling the line negative) to account the memory cell's bipolar nature. Consequently, the decoders must be bipolar. For the negative select switches NMOS devices are used and for the positive select switches PMOS switches are used. To reduce layout area and routing, the negative select switches and positive select switches are separately grouped, with a subset of the positive select switches located between subsets of the negative select switches and vice-versa. The connection for the decoder switches are routed to a central hook-up region for connection to the control lines of the cross-point array.