Memory Write Timing With Delayed Word Line Assertion
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Solution Overview
Problem
Conventional memory cells experience contention during write operations due to simultaneous assertion of bit lines and word lines, leading to increased power consumption, write time, and potential failures.
Innovation Solution
Implementing additional delay circuits that delay the assertion of the word line after bit lines have been pulled down, reducing contention at the storage nodes of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit lines and word lines are asserted simultaneously for write operations, then write operations can be performed, but contention occurs at storage nodes leading to increased power consumption and write failures
Solution Approach 1:
The patent applies preliminary action by asserting the bit line before the word line. Specifically, the bit line is asserted to drive the storage node to a first voltage level, and only after this preliminary action does the word line get asserted to enable the access transistor. This sequencing prevents contention because the storage node is already at the correct voltage level before the access transistor turns on, eliminating the simultaneous assertion problem that causes contention and write failures.
2Power
If bit lines and word lines are asserted simultaneously, then write operations complete quickly, but power consumption increases due to contention currents
Solution Approach 1:
By performing the preliminary action of asserting the bit line first to establish the correct voltage level at the storage node, the patent eliminates contention currents that would otherwise flow when both lines are asserted simultaneously. This reduces power consumption while the total write time remains acceptable since the sequential timing is optimized to minimize delays.
3Speed
If word line is asserted before bit line is fully pulled down, then write operation starts faster, but contention occurs at the storage node
Solution Approach 1:
The patent makes the preliminary action of asserting the bit line complete before asserting the word line. The bit line assertion is designed to fully drive the storage node to the first voltage level (e.g., logic high) before the word line assertion occurs. This ensures that when the access transistor turns on due to word line assertion, the storage node is already at the correct voltage, preventing any contention current flow while maintaining fast write operation speed.
Data Source
AI summary
Memory devices, circuits, and a method of operating the same are disclosed. In one aspect, a memory device includes a memory cell coupled to a bit line and a word line. The memory device includes a first delay circuit configured to generate a first delay signal to activate a word line driver according upon the bit line of the memory cell transitioning to a logic low state. The memory device includes a second delay circuit configured to generate a second delay signal to deactivate the word line driver according to at least an amount of time to assert the word line coupled to the memory cell.