Adjustable Reference Potential Circuit for Multi-DDR Signal Accuracy
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Solution Overview
Problem
In memory products combining different generations and specifications, inaccurate reference potentials affect data signal interpretation.
Innovation Solution
A reference potential generating circuit with upper-potential and lower-potential selection switches, a resistor string, and multiplexers, allowing for adjustable reference potential signals, and a control method to adjust the signal based on edge bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single reference potential signal is used for multiple receiving units, then cost is reduced, but data interpretation accuracy deteriorates when the reference potential is not accurate enough
Solution Approach 1:
The reference potential generating circuit is segmented into multiple independent potential generation paths, each capable of producing reference potentials at different voltage levels. This allows different receiving units to be assigned to different segments with appropriately matched reference potentials, resolving the contradiction between cost reduction and accuracy by providing tailored reference potentials without requiring complete redundancy across all units.
Solution Approach 2:
The circuit incorporates dynamic selection capability through switches and multiplexers that can dynamically assign different reference potential levels to different receiving units based on their specific requirements. This dynamic adaptability allows the system to optimize data interpretation accuracy for each receiving unit while maintaining a unified reference potential generation structure, thus balancing cost efficiency with precision.
2Adaptability or versatility
If reference potential signal levels are adjusted to match different memory generations, then compatibility is improved, but circuit complexity increases
Solution Approach 1:
The reference potential generating circuit is designed with multi-functionality to serve multiple memory generation types and receiving units with different voltage requirements. By incorporating adjustable potential levels and dynamic selection capabilities, a single unified circuit structure can adapt to various memory generations (e.g., DDR3, DDR4, DDR5) without requiring separate dedicated circuits for each generation, thus achieving compatibility while controlling complexity through design integration.
3Device complexity
If multiple receiving units share the same reference potential signal, then device complexity is reduced, but reliability deteriorates when the reference potential is not accurate for all units
Solution Approach 1:
The circuit employs dynamic selection mechanisms that allow each receiving unit to be dynamically assigned to the most appropriate reference potential level based on its specific operational requirements and memory generation type. This dynamic adaptability ensures that each receiving unit operates with an optimized reference potential, maintaining high reliability across diverse units while preserving the benefits of a unified reference potential generation architecture through controlled complexity.
Data Source
AI summary
A reference potential generating circuit includes at least one upper-potential selection switch, at least one lower-potential selection switch, a resistor string and at least one multiplexer. Each upper-potential selection switch receives an upper-voltage signal, and one of the upper-potential selection switches is turned on. Each lower-potential selection switch receives a lower-voltage signal, and one of the lower-potential selection switches is turned on. The resistor string is coupled between the upper-potential selection switch and the lower-potential selection switch. The multiplexer includes a plurality of input ends and an output end. The input ends are coupled to ends of the resistors one to one, and the output end of one of the multiplexers outputs a reference potential signal. A control method for the aforementioned reference potential generating circuit is further provided here.