Scalable Memory Interface Driver With Gate-Voltage Impedance Calibration
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Solution Overview
Problem
Existing memory interface drivers face challenges with increased design area, cost, and resource consumption due to the need for multiple drivers to support different memory interface protocols, leading to issues such as tripling design area and pad capacitance, and limitations in device stress due to varying supply voltages.
Innovation Solution
A scalable multi-voltage memory interface driver circuit that uses a single driver structure with a p-channel metal-oxide-semiconductor (PMOS) and n-channel metal-oxide-semiconductor (NMOS) driver, employing a variable gate voltage generation circuit and stop signal generation circuits to calibrate impedance across different protocols, reducing device stress and pad capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple drivers with different designs are used to support different memory interface protocols, then protocol compatibility is improved, but design area and cost increase significantly
Solution Approach 1:
The patent implements a single driver structure that can operate across multiple voltage domains (0.8V, 1.0V, 1.2V) by using a scalable multi-voltage architecture. The driver uses variable gate voltage generation circuits and calibration mechanisms to adapt to different supply voltages, eliminating the need for separate drivers for each protocol while maintaining protocol compatibility through voltage scaling rather than structural duplication
2Adaptability or versatility
If the number of driver legs is increased to support a wide range of supply voltages, then voltage adaptability is improved, but pad capacitance increases to 1.8 pF affecting maximum data rate
Solution Approach 1:
The patent employs dynamic voltage scaling where the gate voltage of the driver transistors is dynamically adjusted based on the supply voltage domain. Instead of using multiple static driver legs, the system dynamically changes the operating voltage of a single driver structure, thereby maintaining low pad capacitance while achieving wide voltage adaptability and preserving maximum data rate performance
3Reliability
If thick oxide devices are used for higher voltage domain and thin oxide devices for lower voltage domain, then device stress is reduced, but device complexity and design area increase
Solution Approach 1:
The patent changes the voltage parameter dynamically rather than changing the physical device structure. By using a single oxide thickness design that can operate across different voltage domains through gate voltage control and calibration, the patent avoids the complexity of implementing both thick and thin oxide devices while still managing device stress through voltage scaling and calibration mechanisms
4Adaptability or versatility
If N different design IPs are developed to support N different protocols, then protocol support is improved, but design area and cost increase by N times
Solution Approach 1:
The patent creates a universal driver IP that can support multiple protocols (LPDDR5, DDR5, TOGGLE, etc.) through a single scalable multi-voltage design. The driver uses voltage domain adaptation and calibration circuits to accommodate different protocol requirements without requiring separate design IPs, thereby reducing design area and cost while maintaining comprehensive protocol support
Data Source
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AI summary
A circuit for calibrating analog signals on a scalable memory interface driver is provided. The circuit includes: PMOS and NMOS drivers; a variable gate voltage generation circuit; a pull-up stop signal generation circuit; and a pull-down stop signal generation circuit. The circuit is configured to: provide a first variable voltage to the PMOS driver from the variable gate voltage generation circuit; stop the first variable voltage from changing by disconnecting a first current source according to using a pull-up calibration stop signal, based on identifying that the first driver output is greater than a reference value; provide a second variable voltage to the NMOS driver from the variable gate voltage generation circuit; and stop the second variable voltage from changing by disconnecting a second current source according to using a pull-down calibration stop signal, based on the second driver output from the NMOS driver being less than the reference value.