CFET Header Switch Layout for Memory Power and Chip Area
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Solution Overview
Problem
Existing integrated circuits (ICs) with complementary field effect transistor (CFET) devices face challenges in optimizing the resistance ratio and chip area utilization in power management switches, particularly in connecting power lines to memory circuits.
Innovation Solution
Implementing a header switch with a CFET device configuration, where a first transistor is stacked over a second transistor, forming a diode connection, to improve resistance ratio and reduce chip area, allowing power management based on a power control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a header switch is implemented using conventional FET configuration, then power management function is achieved, but the resistance ratio is suboptimal and chip area is increased
Solution Approach 1:
The patent transitions from planar FET configuration to a three-dimensional stacked CFET configuration, where the first FET is vertically stacked over the second FET. This vertical stacking in the third dimension enables improved resistance ratio while reducing the lateral chip area occupied by the header switch.
Solution Approach 2:
The patent combines two FET devices into a single integrated CFET structure by stacking them vertically and sharing common regions (source/drain regions and conductive layers). This merging achieves both functions (power management and improved resistance ratio) within a compact footprint.
2Area of stationary object
If CFET devices are used in power management switches, then chip area is reduced, but device complexity increases
Solution Approach 1:
The CFET device is segmented into distinct functional components: a first FET with gate terminal for power control, a second FET with diode connection, and shared source/drain regions. This segmentation allows independent optimization of each FET's function while maintaining a compact integrated structure.
Solution Approach 2:
The shared source and drain regions between the two FETs serve multiple functions: they act as source for one FET and drain for the other, and provide common electrical connections. This multi-functionality reduces the number of discrete components needed, managing complexity while achieving area reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CFET-based header switch enhances power management efficiency by optimizing resistance ratio and reducing chip area, enabling power supply to memory circuits on an as-needed basis.
Implementation Method 1
complementary field effect transistor (CFET) devices. A CFET device generally has an upper FET overlying a lower FET in a stacked configuration
Data Source
AI summary
An integrated circuit device includes a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of a substrate. The first transistor is stacked over the second transistor. The integrated circuit device also includes a power line connected to a source terminal of the first transistor. The first transistor has a gate terminal configured to receive a control signal and has a drain terminal connected to both a gate terminal and a drain terminal of the second transistor. The integrated circuit device further includes a memory power line connected to a source terminal of the second transistor and a memory circuit configured to receive a supply voltage from the memory power line.