Double-Sided Memory Array With Backside Interconnect Bond Pad Expansion
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Solution Overview
Problem
Existing memory devices face challenges in achieving high storage density and efficient operation due to limitations in the number of bond pads and interconnects, which restrict the arrangement and performance of memory chips.
Innovation Solution
A circuit chip is positioned between two memory chips, connected through both front and backside interconnects, allowing for increased bond pads and flexible component placement, enabling simultaneous operations on memory cells in different chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory chips are stacked with limited bond pads, then device complexity is reduced, but storage density and operational efficiency deteriorate
Solution Approach 1:
The patent utilizes the backside of the circuit chip to create additional interconnect pathways, effectively adding a new dimension to the interconnection architecture. By forming second interconnects through the substrate from the backside, the design doubles the available bond pad connections without increasing the footprint or basic structural complexity, thereby resolving the contradiction between simple structure and high storage density
2Speed
If interconnect length is reduced, then read/write speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the interconnection path into two separate routes: first interconnects extend from the front surface bond pads through the substrate, while second interconnects extend from the backside bond pads through the substrate. This segmentation allows each interconnect to be optimized independently for shorter length and reduced critical path, improving read/write speed while distributing the manufacturing precision requirements across multiple smaller alignment tasks rather than one long interconnect
3Quantity of substance
If bond pads are increased, then storage density and flexibility are improved, but device complexity increases
Solution Approach 1:
The patent resolves the contradiction by utilizing the backside surface of the circuit chip to place additional bond pads and second interconnects. This approach effectively doubles the number of available bond pads without increasing the planar footprint or complicating the front-side architecture. The backside interconnects provide parallel pathways that mirror the front-side connections, increasing capacity while maintaining structural symmetry and managing complexity through dimensional expansion rather than planar crowding
Data Source
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AI summary
Disclosed herein are related to a device comprising a memory chip, another memory chip, and a circuit chip between the memory chip and the another memory chip, where the circuit chip is connected to the memory chip and the another memory chip through different connections. The memory chip may include a first memory array and a first bond pad, and the another memory chip may include a second memory array and a second bond pad. The circuit chip may include a third bond pad on a first surface of the circuit chip coupled to the first bond pad, and a fourth bond pad on a second surface of the circuit chip coupled to the second bond pad. The circuit chip may include a transistor coupled to the third bond pad through a front side connection and another transistor coupled to the fourth bond pad through a backside connection.