Dual Row-Column ECC Memory for Dynamic Data Writes
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Solution Overview
Problem
Existing memory devices with column addressability face significant write amplification and performance degradation due to the need to update multiple column error correction codes (ECC) with each row write, limiting their application to static data and excluding error-tolerant applications like column-oriented databases.
Innovation Solution
Implementing a system that maintains both row and column ECC data simultaneously, using methods such as a column ECC cache or row write cache to minimize the need for frequent updates, thereby reducing write amplification and enhancing performance for dynamic data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If column addressability is implemented with ECC for dynamic data, then data accessibility and versatility are improved, but write amplification increases and performance deteriorates
Solution Approach 1:
The memory system is segmented into row storage units and column storage units, with ECC operations performed separately on each segment. This allows column reads to access data from multiple rows efficiently while maintaining row write performance by updating only the affected column ECC values rather than entire column ECC data.
Solution Approach 2:
A column ECC cache is introduced as an intermediary component that stores column ECC values temporarily. This cache acts as a buffer between the row storage and column ECC computation, allowing fast column reads to proceed without immediately updating column ECC in the main storage, thereby reducing write amplification.
2Reliability
If column ECC is updated with each row write, then data reliability is improved, but write amplification increases
Solution Approach 1:
Column ECC values are pre-computed and cached before being written to the main storage. When a row write occurs, the system updates only the specific column ECC values that are affected by the change, rather than rewriting all column ECC data. This preliminary caching approach maintains data reliability while minimizing the amount of data that needs to be rewritten.
Solution Approach 2:
Instead of uniformly updating all column ECC data with each row write, the system selectively updates only the local column ECC values that are actually affected by the row write operation. This localized update approach maintains data reliability for the modified columns while avoiding unnecessary writes to unchanged columns.
3Productivity
If column addressability is implemented without ECC, then write performance is improved, but error correction capability is lost
Solution Approach 1:
The memory system dynamically switches between row-oriented and column-oriented access modes, with ECC operations adapted to the current mode. In row write mode, standard row ECC is used with high performance. In column read mode, the system retrieves column data and applies column ECC from the cache, providing error correction capability while maintaining good performance through the dynamic adaptation to access patterns.
Data Source
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AI summary
Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.