3D Memory Structure With Through-Openings for Dense WL Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor memory devices is to achieve higher storage density and smaller feature size while simplifying wiring design and manufacturing processes, particularly in DRAMs, where integrating more memory cells in a unit area and reducing the area occupied by each device is crucial.
Innovation Solution
A memory structure is designed with multiple memory layers stacked on a control circuit layer, where Word Lines (WLs) are connected through openings that go through each other, allowing for a three-dimensional structure that reduces horizontal area occupation and simplifies wiring and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are integrated in higher density with smaller feature size, then storage capacity is improved, but wiring design and manufacturing process complexity increases
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional stacked memory structure. Multiple memory layers are vertically stacked above each other, with word lines extending through multiple layers via openings. This dimensional change allows significantly more memory cells to be packed into the same footprint area while using shared word line structures that pass through all layers, thereby reducing the complexity of individual layer wiring design.
Solution Approach 2:
The word lines are designed to serve multiple functions across multiple memory layers simultaneously. A single word line structure extends through openings in multiple memory layers, enabling the same control circuit to address memory cells in different layers. This multi-functionality reduces the total number of independent word line structures needed, simplifying the overall wiring design and manufacturing process while increasing storage density.
2Quantity of substance
If more memory cells are integrated in a unit area, then storage capacity is improved, but area occupied by each device increases
Solution Approach 1:
The patent utilizes vertical stacking of multiple memory layers to increase storage density without proportionally increasing the horizontal footprint area. By arranging memory cells in three dimensions rather than two, the device achieves higher capacity within a compact form factor, effectively moving the scaling challenge from the lateral dimension to the vertical dimension where more layers can be stacked.
3Quantity of substance
If three-dimensional stacked structure is implemented, then integration density is improved, but manufacturing process complexity increases
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete memory layers that can be fabricated and processed independently to some extent. Each layer contains complete memory cell structures that can be formed using standard planar processing techniques, and then the layers are stacked and interconnected. This segmentation allows the complex 3D structure to be built from simpler, more manufacturable components, reducing overall manufacturing complexity while achieving high integration density.
Data Source
AI summary
A memory includes a substrate, a control circuit layer located in the substrate, and at least two memory structure layers. The control circuit layer includes at least part of control circuits of the memory. The at least two memory structure layers are sequentially stacked on the control circuit layer. Each memory structure layer includes multiple memory blocks arranged in an array. The memory block includes multiple parallel Word Lines (WLs) extending in a first direction. The first direction is parallel to a surface of the substrate. An opening is provided between adjacent memory blocks located in the same memory structure layer. The openings located in different memory structure layers go through each other. WLs in the at least one memory structure layer are connected to the control circuit layer through the openings that go through each other.