MRAM Read Biasing for Low-Leakage Cell State Sensing
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Solution Overview
Problem
Conventional magneto resistive memory devices suffer from low reliability and high power consumption due to high leakage currents and low Ion/Ioff ratios, making it difficult to discriminate the state of a selected memory cell from unselected cells, especially at higher temperatures.
Innovation Solution
A method involving a novel polarization of selection transistors with a first voltage applied to the bit line and a second voltage applied to the source line, combined with a NMOS transistor configuration, reduces leakage currents and enhances the Ion/Ioff ratio, allowing for reliable read operations with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional magneto resistive memory devices use standard selection transistor polarization, then the device structure is simple, but leakage currents are high and Ion/Ioff ratio is low
Solution Approach 1:
The patent applies parameter changes by reversing the voltage polarization of the selection transistor from conventional (source at lower potential, drain at higher potential) to inverted (source at higher potential, drain at lower potential). This parameter change in voltage polarity fundamentally alters the transistor's electrical characteristics, reducing leakage current by over 2000 times and achieving an Ion/Ioff ratio greater than 10^6, thereby resolving the contradiction between reliability and power consumption
2Measurement precision
If conventional read operations are performed with standard transistor polarization, then the device structure remains simple, but leakage currents mask the read current making cell state discrimination difficult
Solution Approach 1:
The patent changes the electrical parameter of the selection transistor by inverting its voltage polarization. This parameter change reduces the leakage current to such an extent that it no longer masks the read current, enabling precise discrimination of the selected cell's state even in the presence of leakage from unselected cells, thus achieving high measurement precision
3Reliability
If standard selection transistor configuration is used, then manufacturing is straightforward, but the Ion/Ioff ratio is low making reliable reads difficult
Solution Approach 1:
The patent achieves high reliability through parameter changes in the transistor's electrical configuration rather than structural modifications. By simply inverting the voltage application (applying higher voltage to source and lower voltage to drain), the Ion/Ioff ratio exceeds 10^6 without requiring new transistor designs or manufacturing processes, maintaining ease of manufacture while dramatically improving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method significantly reduces leakage currents, improving the Ion/Ioff ratio by over 2000 times, ensuring reliable read operations with minimal power consumption and maintaining the memory array's dimensions.
Implementation Method 1
The resistance value between the pinned layer 2c and the free layer 2b is dependent on the actual state of the free layer magnetization orientation. When the free layer 2b and the pinned layer 2c have parallel magnetizations, the magnetic tunnel junction presents a relatively lower electric resistance, whereas in the antiparallel magnetizations the magnetic tunnel junction presents a relatively higher electric resistance.
Implementation Method 2
a spin orbit torque (SOT) memory cell. In this respect the MTJ 2 lies on a SOT layer, as this is well known in the art.
Data Source
AI summary
A magneto resistive memory device including a memory array with at least one bit line (BL) and at least one source line (SL, SLB), the bit line (BL) and the at least one source line (SL, SLB) associated with a plurality of memory cells each presenting a magnetic tunnel junction and each presenting at least one selection transistor (RT) to selectively connect the bit line (BL). The memory array also includes a peripheral block configured to apply a first voltage (Vread) greater than ground voltage (Vss) on the bit line (BL) and applying a second voltage (VSL) greater than the first voltage (Vread) on the at least one source line (SL, SLB). The state stored in the selected cell is detected by using a sense amplifier (SA) of the peripheral block associated with the at least one bit line (BL) to sense the current flowing in the bit line (BL).