Dual-Ported DRAM Interface Layout for High-Density RDIMMs
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Solution Overview
Problem
Conventional memory systems are limited to one or two modules at maximum signaling rates due to degraded signaling integrity when more modules are added, restricting the maximum number of modules a single memory channel can support.
Innovation Solution
Implementing a point-to-point interconnect topology with dual-ported DRAM components and additional data interfaces to enable higher module counts and ranks, allowing for increased capacity without reducing signaling rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more modules are added to the memory system, then the memory capacity increases, but the signaling integrity degrades
Solution Approach 1:
The patent introduces buffer chips as intermediary components between the memory modules and the memory channel. These buffers act as mediators that receive, condition, and retransmit signals, thereby maintaining signaling integrity even when multiple modules are connected. The buffer chips compensate for signal degradation by providing signal regeneration and impedance matching, enabling higher module counts without sacrificing reliability.
Solution Approach 2:
The memory system is segmented into multiple functional blocks: memory modules, buffer chips, and memory channel. By dividing the system into discrete segments with defined interfaces, the patent enables independent optimization of each component. The buffer chips serve as intermediate segments that isolate the memory modules from direct connection to the memory channel, allowing capacity expansion while maintaining signal quality through staged signal processing.
2Speed
If the signaling rate is increased to improve performance, then the data transfer speed increases, but the maximum number of supported modules decreases
Solution Approach 1:
Buffer chips are introduced as intermediary components that enable high-speed signaling to be maintained across multiple modules. The buffers receive high-rate signals from the memory channel, perform conditioning and regeneration, and forward signals to multiple memory modules. This intermediary approach allows the memory channel to operate at high signaling rates while supporting an increased number of modules through the buffering capability.
Solution Approach 2:
The system employs dynamic signal conditioning in the buffer chips, where signal parameters such as amplitude, timing, and impedance are dynamically adjusted based on the number and configuration of connected modules. This dynamic adaptation enables the system to maintain optimal signaling rates regardless of the module count, allowing flexible configuration from single-module to multi-module deployments without sacrificing performance.
3Reliability
If buffer chips are added for both command/address bus and data bus, then the signaling integrity is maintained, but the device complexity increases
Solution Approach 1:
The buffer chips are designed with multi-functional capability, handling both command/address bus signals and data bus signals through the same physical component. This universal buffer design consolidates what would otherwise require separate buffering components for different signal types, reducing overall device complexity while maintaining signaling integrity across all bus interfaces. The single buffer chip performs multiple functions: command buffering, data buffering, and signal conditioning for various signal types.
4Quantity of substance
If dual-ported DRAM components are used, then the capacity and bandwidth requirements are met, but the manufacturing complexity increases
Solution Approach 1:
The dual-ported DRAM functionality is segmented into separate physical components: standard DRAM memory components and dual-ported buffer components. This segmentation allows the majority of memory components to remain simple, single-ported devices that are easier to manufacture, while only the buffer components require the more complex dual-ported architecture. The segmentation enables high capacity and bandwidth through the dual-ported buffers without requiring all memory components to be complex dual-ported devices.
Data Source
AI summary
The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.