Shared Word-Line Read Assist Circuit for SRAM SNM Stability

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Solution Overview

Problem

The reliability of Static Noise Margin (SNM) in SRAM devices is deteriorating in advanced technology nodes, and existing read assist techniques like lowering word line voltage require additional transistors, increasing the WL driver area and causing performance penalties.

Innovation Solution

A new structural circuit is introduced that allows pull down circuits to be shared between adjacent word lines, reducing the area and loading of these circuits, and utilizing transistors to adjust word line voltages efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional transistors are added to lower word line voltage for read assist, then read assist capability is improved, but WL driver area increases

Engineering Contradiction:

ImproveStatic Noise MarginVSAvoidWL driver area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the pull-down circuit functionality across multiple word lines by sharing common transistors (PD1A/PD1B for WL1/WL2, PD2A/PD2B for WL3/WL4). This consolidation reduces the total transistor count and area required compared to having dedicated pull-down circuits for each word line, while still providing the necessary read assist capability to maintain Static Noise Margin.

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If additional transistors are added to lower word line voltage for read assist, then read assist capability is improved, but device complexity increases

Engineering Contradiction:

ImproveStatic Noise MarginVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent reduces device complexity by combining pull-down circuit resources. Instead of implementing separate pull-down circuits for each word line, the design shares transistors between adjacent word lines, reducing the total component count and simplifying the overall circuit structure while maintaining read assist functionality.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared pull-down transistors serve multiple word lines simultaneously, providing multi-functionality. For example, transistors PD1A and PD1B are used to control voltage levels for both WL1 and WL2, making the circuit more efficient and less complex than dedicated per-word-line circuits.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Manufacturing precision

If pull down circuits are duplicated for each word line, then voltage control precision is improved, but area and loading increase

Engineering Contradiction:

Improvevoltage control precisionVSAvoidpull down circuit area

Core Design Contradiction:

Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent combines pull-down circuit resources to serve multiple word lines, reducing area by up to 50% compared to duplicated circuits. The shared transistors are sized and configured to provide adequate voltage control precision for multiple word lines simultaneously, avoiding the need for full duplication.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20260065983A1Read assist circuit for memory device and operation method thereof

Publication Date: 2026.03.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory device is provided, including a first word line coupled to a first memory cell, a second word line coupled to a second memory cell, and a read assist circuit coupled between the first and second word lines, and in a first time period configured, in response to a first control signal, to adjust a voltage level of the first word line to a first voltage and to adjust a voltage level of the second word line to a second voltage. In some embodiments, the first voltage is smaller than a first supply voltage, and the second voltage is greater than a second supply voltage smaller than the first supply voltage.