Sketch Circuit Refresh Binning for DRAM Power Reduction
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Solution Overview
Problem
Volatile memory devices, such as DRAM, face inefficiencies in refresh operations due to varying decay rates of memory cells, leading to unnecessary refresh cycles and increased power consumption, as existing methods refresh all cells based on the fastest decay rate without efficient binning strategies.
Innovation Solution
The implementation of a sketch circuit for refresh binning, which uses multiple hash functions to group memory rows into bins based on decay rates, allowing for differential refresh frequencies, reducing unnecessary refresh cycles and optimizing power usage by refreshing 'weak' rows more frequently than 'normal' rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory cells are refreshed based on the fastest decay rate, then information loss is prevented, but power consumption increases and refresh efficiency decreases
Solution Approach 1:
The patent segments memory rows into different bins based on their decay characteristics. Weak rows (with faster decay) are separated from normal rows (with slower decay) using hash functions that map row addresses to different bin identifiers. This segmentation allows differential refresh strategies: weak rows are refreshed more frequently while normal rows are refreshed less frequently, preventing unnecessary refresh operations and reducing power consumption while maintaining information integrity for all rows
Solution Approach 2:
The patent applies local quality by assigning different refresh frequencies to different memory row bins based on their specific decay characteristics. Instead of applying a uniform refresh rate to all rows, the system tailors the refresh quality (frequency) to each bin's local needs. Weak rows receive higher refresh frequency (better quality) while normal rows receive lower refresh frequency, optimizing the balance between reliability and power consumption for each segment
2Reliability
If all memory cells are refreshed based on the fastest decay rate, then information loss is prevented, but refresh operation time increases
Solution Approach 1:
The patent segments memory rows into different bins based on their decay characteristics. Weak rows (with faster decay) are separated from normal rows (with slower decay) using hash functions that map row addresses to different bin identifiers. This segmentation allows differential refresh strategies: weak rows are refreshed more frequently while normal rows are refreshed less frequently, preventing unnecessary refresh operations and reducing power consumption while maintaining information integrity for all rows
Solution Approach 2:
The patent applies partial action by refreshing only the necessary portion of memory rows at each refresh cycle. Instead of refreshing all rows uniformly, the system identifies and refreshes only the weak rows that require attention based on their bin assignment. This partial refresh approach reduces the total time spent on refresh operations while still preventing information loss in the critical weak rows
3Device complexity
If uniform refresh rate is applied to all memory rows, then implementation is simple, but refresh efficiency decreases
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing bin assignments for each memory row before actual refresh operations. Hash functions are used to determine which bin each row belongs to, and this bin information is stored in advance. During refresh operations, the system simply queries the pre-computed bin information to determine refresh frequency, avoiding complex real-time decay rate measurements and simplifying the refresh control logic while enabling efficient differential refresh
Data Source
AI summary
Apparatuses, systems, and methods for sketch circuits for refresh binning. The rows of a memory may have different information retention times. The row addresses may be sorted into different bins based on these information retention times. In order to store information about which row addresses are associated with which bins a sketch circuit may be used. When an address is generated as part of a refresh operation, it may be used to generate a number of different hash values, which may be used to index entries in a storage structure. The entries may indicate which bin the address is associated with. Based on the binning information, the memory may refresh the address at different rates (e.g., by determining whether to provide the address as a refresh address or not).