Memory Array Interconnect Layout for Uniform Cell Resistance
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Solution Overview
Problem
Existing memory devices using variable resistance elements face challenges in efficiently managing interconnect resistance variations due to varying distances between memory cells, which affect operational efficiency and reliability.
Innovation Solution
The memory device incorporates a configuration with global interconnects of varying lengths to balance interconnect resistance by connecting local interconnects through switch circuits, ensuring shorter lengths for global interconnects relative to local ones, thereby stabilizing resistance across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a large array, then storage capacity increases, but interconnect resistance variations increase due to varying distances
Solution Approach 1:
The memory device is divided into multiple banks, with each bank containing a subset of memory cells. This segmentation allows the interconnect structure to be optimized for smaller regions, reducing resistance variations within each bank while maintaining large total storage capacity across all banks.
Solution Approach 2:
Different interconnect lengths are assigned to different memory cells based on their specific positions and access patterns. Hot memory cells (frequently accessed) are connected via shorter interconnects to minimize resistance, while cold memory cells use longer interconnects, thereby optimizing overall system performance.
2Reliability
If all memory cells use equal-length interconnects, then resistance uniformity improves, but distance to memory cells increases for some cells
Solution Approach 1:
The patent implements non-uniform interconnect lengths tailored to the specific access frequency and position of memory cells. Frequently accessed memory cells are positioned closer to the interconnect origin with shorter connection lengths, reducing resistance for critical operations.
Solution Approach 2:
The system dynamically manages interconnect usage based on memory cell access patterns. Hot memory cells utilize shorter interconnects for rapid access, while cold memory cells use longer interconnects, allowing the system to adapt to varying workload requirements.
3Speed
If shorter global interconnects are used, then resistance decreases and speed increases, but coverage area reduces
Solution Approach 1:
The memory array is divided into multiple banks, each served by dedicated shorter interconnects. This allows each bank to be accessed quickly via short connections while the overall system maintains large coverage through the combined capacity of multiple banks.
Solution Approach 2:
The patent extends the memory structure into the vertical dimension with multiple stacked memory cell arrays. Short interconnects access memory cells in the same bank, while bank switching enables access to other banks, effectively increasing coverage without increasing interconnect length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively mitigates interconnect resistance variations, enhancing operational stability and efficiency of the memory device by equalizing resistance across memory cells.
Implementation Method 1
A memory device using a variable resistance element (for example, a magneto resistive effect element) as a memory element is known
Data Source
AI summary
According to one embodiment, a device includes: an array including a first interconnect extending in a first direction, second and third interconnects extending in a second direction, a first cell between the first and second interconnects, and a second cell between the first and third interconnects; a first switch circuit connected to the first interconnect; a second switch circuit connected to the second and third interconnects; first and second global interconnects connected between the second switch circuit and a first circuit, the second interconnect is disposed between the first switch circuit and the third interconnect in the first direction, the second interconnect is connected to the first global interconnect via the second switch circuit, the third interconnect is connected to the second global interconnect via the second switch circuit, and a length of the second global interconnect is shorter than a length of the first global interconnect.