Memory Wiring Layout for Balanced Control Signal Delay
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Solution Overview
Problem
The challenge of minimizing the area for laying out wiring in semiconductor devices while ensuring high transmission performance, particularly in the row decoding region, is exacerbated by insufficient space due to reduced layout space for wiring, leading to increased complexity and resource demands.
Innovation Solution
A wiring structure is designed with a signal processing unit and a first transmission unit that separately transmits an initial control signal to first and second column decoding regions, ensuring a delay difference within a preset threshold, allowing for reduced space by processing and re-processing signals in each region, and incorporating shield lines to minimize electrical interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the area for laying out the row decoding region is reduced to minimize chip area, then the space for wiring is further reduced, but the transmission performance of the wiring may be affected
Solution Approach 1:
The patent utilizes three-dimensional wiring structures and multi-layer interconnects to route signals vertically and diagonally across the chip, transforming the traditional two-dimensional wiring layout into a three-dimensional architecture. This allows signals to bypass congested horizontal routing paths and reduces the horizontal space required for the row decoding region while maintaining adequate transmission performance through optimized 3D signal paths.
Solution Approach 2:
The row decoding region is divided into multiple sub-regions or functional blocks that can be independently routed and optimized. By segmenting the decoding logic and distributing it across different areas of the chip, the patent reduces the concentration of wiring in any single location, thereby minimizing the overall space required while maintaining signal integrity through localized routing segments.
2Area of stationary object
If the space for wiring is reduced to minimize chip area, then the layout complexity increases, but the transmission performance must be maintained
Solution Approach 1:
The patent implements shared wiring resources and multiplexed signal paths where the same physical wiring structures serve multiple functions and multiple signal routes. For example, differential signal pairs are routed through shared shielded corridors, and control signals are multiplexed onto common interconnects that serve multiple decoding functions, thereby reducing overall wiring space while managing complexity through standardized multi-functional routing blocks.
Solution Approach 2:
The patent employs variable wiring parameters such as adjustable trace widths, impedance-controlled routing, and dynamic signal switching to optimize the use of limited wiring space. By changing electrical parameters like signal voltage levels, timing characteristics, and impedance matching, the design achieves reliable transmission performance in compressed wiring configurations without proportionally increasing layout complexity.
3Area of stationary object
If the wiring space is minimized, then the number of shield lines required is reduced, but electrical interference may increase
Solution Approach 1:
The patent introduces intermediate shielding structures and ground reference planes that act as mediators between adjacent signal lines. These intermediary elements are strategically placed at critical transition points and signal crossings to provide localized electromagnetic shielding without requiring continuous shield lines throughout the entire wiring path, thereby reducing overall wiring space while maintaining protection against electrical interference through targeted intermediary shielding.
Data Source
AI summary
The present disclosure provides a wiring structure of a memory and a memory. The wiring structure includes: a first operation unit configured to receive an initial control signal and a first enable signal and generate a first control signal; a second operation unit configured to receive the initial control signal and a second enable signal and generate a second control signal; a signal processing unit configured to receive and process the initial control signal, the first enable signal, and the second enable signal separately; and a first transmission unit, where the first transmission unit and the signal processing unit are jointly configured to: transmit the initial control signal to the first operation unit and the second operation unit separately, and ensure that a difference between delays of the initial control signals received by the first operation unit and the second operation unit separately is less than a preset threshold.