Multi-Voltage Memory Driver Calibration With Variable Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory interface drivers face challenges with increased design area, cost, and resource consumption due to the use of multiple drivers for different protocols, leading to issues like tripling design area, pad capacitance, and device stress across varying supply voltages.
Innovation Solution
A circuit for a scalable multi-voltage memory interface driver that uses a single driver structure with a p-channel metal-oxide-semiconductor (PMOS) and n-channel metal-oxide-semiconductor (NMOS) driver, employing a variable gate voltage generation circuit and stop signal generation circuits to calibrate impedance, allowing a single driver to support multiple protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple drivers with different designs are used to support different memory interface protocols, then protocol compatibility is improved, but design area and cost increase significantly
Solution Approach 1:
The patent implements a single driver structure that can operate across multiple voltage domains (1.05V, 1.2V, 0.5V) by dynamically adjusting the gate voltage of PMOS and NMOS transistors. This universal driver replaces multiple protocol-specific drivers, achieving support for LPDDR5, DDR5, and other memory interfaces without increasing design area
Solution Approach 2:
The patent changes the electrical parameters (gate voltage) of the driver transistors to adapt to different supply voltages. By varying the gate voltage of PMOS and NMOS devices, the driver impedance is adjusted to match different protocol requirements, enabling a single driver to serve multiple protocols
2Adaptability or versatility
If the number of driver legs is increased to support a wide range of supply voltages, then voltage adaptability is improved, but pad capacitance increases to 1.8 pF affecting maximum data rate
Solution Approach 1:
Instead of increasing the number of driver legs, the patent changes the gate voltage parameter of existing driver transistors to achieve voltage adaptability. This approach maintains the original driver leg count and associated pad capacitance, preserving the maximum data rate while still supporting multiple supply voltages
3Reliability
If thick oxide devices are used for higher voltage domain, then device reliability is improved, but device stress increases when used for lower voltage domain
Solution Approach 1:
The patent changes the gate voltage parameter to operate thick oxide devices across different voltage domains. By adjusting the gate voltage, the device operates in appropriate regions that maintain reliability at higher voltages while minimizing stress at lower voltages, eliminating the need for separate thin oxide devices
4Adaptability or versatility
If N different design IPs are developed to support N different protocols, then protocol support is improved, but design area and cost increase by N times
Solution Approach 1:
The patent creates a universal driver IP that can support multiple memory interface protocols (LPDDR5, DDR5, TOGGLE, etc.) through dynamic voltage adjustment. This single multi-functional IP replaces N separate protocol-specific IPs, reducing design complexity and area by a factor of N while maintaining full protocol support
Data Source
AI summary
A circuit for calibrating analog signals on a scalable memory interface driver is provided. The circuit includes: PMOS and NMOS drivers; a variable gate voltage generation circuit; a pull-up stop signal generation circuit; and a pull-down stop signal generation circuit. The circuit is configured to: provide a first variable voltage to the PMOS driver from the variable gate voltage generation circuit; stop the first variable voltage from changing by disconnecting a first current source according to using a pull-up calibration stop signal, based on identifying that the first driver output is greater than a reference value; provide a second variable voltage to the NMOS driver from the variable gate voltage generation circuit; and stop the second variable voltage from changing by disconnecting a second current source according to using a pull-down calibration stop signal, based on the second driver output from the NMOS driver being less than the reference value.