DRAM Multi-Voltage Domains for Lower Logic Power
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Solution Overview
Problem
High power consumption in dynamic random access memory (DRAM) devices is primarily attributed to the formula P=CV^2f, where P is power consumption, C is capacitance, V is the switching voltage, and f is the switching frequency, necessitating a reduction in switching voltage to reduce power consumption.
Innovation Solution
Operating the dynamic memory array with a bitline voltage greater than the operating voltage of the digital logic circuitry, using lower voltage swing digital logic for non-storage array logic, and employing voltage-controlled power supplies to manage signal swings in sense amplifiers and switches, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the switching voltage is reduced to lower power consumption, then power consumption decreases, but the signal swing capability and voltage headroom for digital logic circuitry are reduced
Solution Approach 1:
The patent divides the DRAM device into multiple voltage domains: a first voltage domain for the memory array with higher voltage (VBL) for adequate signal swing, and a second voltage domain for digital logic circuitry with lower voltage (VDD) for reduced power consumption. This segmentation allows each domain to operate at its optimal voltage level independently.
Solution Approach 2:
Different voltage levels are applied to different parts of the device according to their specific requirements. The memory array operates at higher voltage to maintain signal integrity during read/write operations, while the digital logic circuitry operates at lower voltage to minimize dynamic power consumption, as described by P=CV²f.
2Reliability
If higher voltage is used in the memory array to maintain signal swing, then signal integrity is improved, but overall power consumption increases
Solution Approach 1:
The device is segmented into voltage domains, allowing the memory array to use higher voltage (VBL) for reliable signal operation while digital logic uses lower voltage (VDD), thus maintaining signal integrity only where necessary.
Solution Approach 2:
The patent changes the voltage parameter locally in different circuit regions. The memory array uses higher voltage to ensure signal integrity during bitline switching and sense amplifier operation, while digital logic blocks use lower voltage to reduce power consumption, optimizing the voltage parameter according to functional requirements.
Data Source
AI summary
A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.