Selector Layer Memory Cell Structure for Lower Hold Current
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing the hold current of selector layers, which can lead to oscillation phenomena and operation failures due to the difficulty in controlling the thickness of resistive layers and maintaining stable conductive states.
Innovation Solution
A semiconductor device design incorporating a resistive layer with a specific resistance and a selector layer that exhibits threshold switching, along with a memory layer, is fabricated by etching a sacrificial pattern and insulating patterns to form a stacked structure, where the etch rates of the insulating patterns decrease with distance, allowing for reduced hold current without increasing the resistive layer thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the resistive layer is increased to reduce hold current, then the hold current decreases, but the manufacturing precision deteriorates due to difficulty in controlling the thickness
Solution Approach 1:
A sacrificial pattern is introduced as an intermediary element to indirectly control the thickness of the resistive layer. The sacrificial pattern is formed with a specific thickness, and the resistive layer is formed to have the same thickness as the sacrificial pattern. By controlling the sacrificial pattern's thickness, the resistive layer's thickness is precisely controlled without direct measurement and adjustment, thus resolving the manufacturing precision issue while achieving hold current reduction.
Solution Approach 2:
The sacrificial pattern is formed in advance before the resistive layer is deposited. This preliminary action establishes a thickness reference that guides the subsequent resistive layer formation process, ensuring precise thickness control from the outset rather than requiring post-processing adjustments.
2Stability of the object's composition
If the thickness of the resistive layer is increased to maintain stable conductive states, then the stability improves, but the device complexity increases
Solution Approach 1:
The sacrificial pattern serves as a mediator that simplifies the overall device structure by providing a pre-defined thickness template. This eliminates the need for complex thickness control mechanisms or multiple adjustment layers, maintaining structural simplicity while ensuring stable conductive states through precise thickness control.
3Reliability
If the hold current is reduced to minimize oscillation, then the operational reliability improves, but the write and read currents must be increased
Solution Approach 1:
The thickness parameter of the resistive layer is changed (increased) to alter its electrical characteristics. By increasing the thickness, the hold current is reduced to minimize oscillation, while the material composition and resistivity are optimized to maintain efficient write and read operations, thus balancing the power requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers the hold current of the selector layer, minimizing oscillation and operation failures by ensuring stable conductive states and facilitating higher write and read currents, thereby enhancing the operational reliability of the memory cells.
Implementation Method 1
a selector layer disposed over the resistive layer and structured to perform a threshold switching by exhibiting different electrically conductive states in response to an applied voltage relative to a threshold voltage
Implementation Method 2
performing an etching operation on the sacrificial pattern and the first to Nth insulating patterns; forming a hole by removing an etched sacrificial pattern on which the etching operation is performed
Data Source
AI summary
Semiconductor devices and fabrication methods of semiconductor devices are disclosed. In an embodiment, a semiconductor device May include a plurality of memory cells, and each of the plurality of memory cells may include: a resistive layer including a material having a specific resistance and including a lower portion and an upper portion disposed over the lower portion, wherein a width of the lower portion is smaller than a width of an uppermost surface of the upper portion; a selector layer disposed over the resistive layer and structured to perform a threshold switching by exhibiting different electrically conductive states in response to an applied voltage relative to a threshold voltage; and a memory layer disposed over the selector layer and structured to store data.