DRAM Row Decoder Power Gating for Standby Loss Reduction
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Solution Overview
Problem
High power consumption in dynamic random-access memory (DRAM) devices due to dynamic and static power consumption, particularly in high capacity and high performance DRAMs, is a challenge that existing technologies have not adequately addressed.
Innovation Solution
A memory device with a power gating switch circuit that selectively interrupts power supply to specific circuits, such as row and column decoders, based on control signals, reducing power consumption by placing these circuits in a powered-off state during non-operation periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply is continuously provided to word line driver circuits and column selection line drivers, then operational reliability is maintained, but power consumption increases due to static leakage current
Solution Approach 1:
The power supply network is segmented into multiple independent paths, each controlled by separate power gating switches. Word line driver circuits and column selection line drivers are divided into different groups (first group and second group), allowing selective power interruption to specific segments while maintaining power to others, thus reducing overall power consumption without compromising operational reliability.
Solution Approach 2:
The power supply state of different circuit groups is dynamically adjusted based on operational requirements. Power gating switches enable real-time switching between powered-on and powered-off states for different circuit groups, allowing the system to adapt power distribution to actual operational needs and minimize static power consumption during non-operational periods.
2Loss of energy
If power gating switch circuits are added to selectively interrupt power supply, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The power gating control is segmented into multiple independent switch circuits, each managing specific circuit groups. This modular approach allows for systematic power management while keeping each individual switch circuit relatively simple in structure, balancing the trade-off between power reduction capability and overall device complexity.
3Speed
If DRAM operates at higher frequency for higher performance, then processing speed improves, but dynamic power consumption increases
Solution Approach 1:
Instead of continuous high-frequency operation of all circuits, the patent implements periodic activation of different circuit groups based on operational demands. Power gating switches enable circuits to be activated only when needed and deactivated during idle periods, reducing dynamic power consumption while maintaining high processing speed during active operations.
Data Source
AI summary
A memory device that selectively interrupts power supply to a circuit performing a single operation includes a power source line, a ground source line, a power gating switch circuit, and a row decoder including word line driver circuits. The word line driver circuits include a first group and a second group based on a first most significant bit (MSB) signal among decoded row addresses. The power gating switch circuit connects the power source line and the ground source line to a first power supply voltage line and a first ground voltage line, respectively, of word line driver circuits in the first group in response to a first control signal and connects the power source line and the ground source line to the first power supply voltage line and the first ground voltage line, respectively, of word line driver circuits in the second group in response to a second control signal.