LUT-Free Memory Repair Using Permanent-State Fault Marking
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Solution Overview
Problem
Existing memory devices that use lookup tables (LUTs) for memory repair suffer from increased latency, power consumption, and limited repair efficiency, particularly in bitwise memory repair, which degrades memory density and requires significant IC chip area.
Innovation Solution
A LUT-free dynamic memory allocation process that uses a permanent state to flag abnormal memory cells, allowing bitwise memory repair without a lookup table, reducing latency and power consumption while increasing memory density and repair efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lookup table (LUT) is used for memory repair, then memory repair capability is provided, but latency increases and power consumption increases
Solution Approach 1:
The patent extracts and removes the lookup table (LUT) component from the memory repair system. By eliminating the LUT, the invention achieves memory repair capability through alternative means (bitwise repair mechanisms) while avoiding the latency and power consumption penalties associated with LUT-based approaches.
Solution Approach 2:
The patent segments the memory repair process into bitwise operations rather than requiring holistic LUT lookups. This segmentation allows repair operations to be performed on individual bits or small groups of bits independently, significantly reducing the time and power required compared to traditional LUT-based repair that requires accessing and processing entire repair tables.
2Reliability
If a lookup table (LUT) is used for memory repair, then memory repair capability is provided, but power consumption increases
Solution Approach 1:
The patent extracts and removes the lookup table (LUT) component from the memory repair system. By eliminating the LUT, the invention achieves memory repair capability through alternative means (bitwise repair mechanisms) while avoiding the power consumption penalties associated with LUT-based approaches.
Solution Approach 2:
The patent segments the memory repair process into bitwise operations rather than requiring holistic LUT lookups. This segmentation allows repair operations to be performed on individual bits or small groups of bits independently, significantly reducing the power required compared to traditional LUT-based repair that requires accessing and processing entire repair tables.
3Reliability
If bitwise memory repair is implemented with LUT, then repair capability is provided, but memory density decreases and IC chip area increases
Solution Approach 1:
The patent extracts and removes the lookup table (LUT) component from the memory repair system. By eliminating the LUT, the invention achieves memory repair capability through alternative means (bitwise repair mechanisms) while avoiding the area overhead associated with LUT storage structures.
Solution Approach 2:
The patent segments the memory repair process into bitwise operations rather than requiring holistic LUT lookups. This segmentation allows repair operations to be performed on individual bits or small groups of bits independently, significantly reducing the area required for repair circuitry while maintaining high repair efficiency.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).