Stacked Memory Clock Transmission with Local TSV Buffering
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Solution Overview
Problem
As the number of chips in a stacked memory device increases, the parasitics in through-silicon vias (TSVs) carrying clock signals become significant, leading to impractical or impossible increases in transmitter size, which degrades clock performance, especially in stacks taller than four chips.
Innovation Solution
Implementing multiple local TSVs with a daisy-chained buffer topology for clock distribution, where each rank receives a clock signal via a receiver and retransmits it through a local TSV, using buffers to manage signal loading and incorporating clock retuning circuitry to synchronize clock timings across ranks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single TSV spans the depth of the stack to carry clock signals to all chips, then clock distribution is achieved, but TSV parasitics increase with each added chip making transmitter size increases impractical or impossible
Solution Approach 1:
The patent divides the single long TSV into multiple shorter local TSVs, each serving a specific rank. Each local TSV has fewer parasitics compared to a single spanning TSV. The clock signal is segmented and distributed through multiple independent TSV paths rather than one overloaded path.
Solution Approach 2:
The patent transitions from a vertical single-path distribution (one TSV spanning all chips) to a multi-dimensional distributed architecture where multiple TSVs are arranged spatially to serve different ranks. This dimensional change allows parallel clock distribution paths.
2Power
If transmitter size is increased to overcome TSV parasitics, then clock signal strength is improved, but TSV loading increases with diminishing returns
Solution Approach 1:
The patent segments the clock distribution into multiple local TSVs, each carrying the signal to a specific rank. This segmentation reduces the effective loading on each TSV compared to a single spanning TSV, allowing transmitters to operate at optimal sizes without excessive power consumption or energy loss.
Solution Approach 2:
Each local TSV is optimized for its specific rank with appropriate transmitter sizing. Instead of one oversized transmitter for the entire stack, each rank receives a clock signal through a locally-optimized TSV connection, reducing overall system power and energy loss.
3Reliability
If multiple local TSVs with daisy-chained buffers are used for clock distribution, then signal degradation is reduced, but device complexity increases
Solution Approach 1:
The clock distribution is segmented into multiple independent local TSV connections, each serving a specific rank. This segmentation reduces signal degradation on each individual TSV path while the overall architecture remains systematic and manageable through modular replication.
Solution Approach 2:
Buffers are introduced as intermediary elements in the daisy-chained topology. These buffers actively regenerate the clock signal at each rank, preventing signal degradation over long distances while maintaining a relatively simple overall architecture through systematic replication.
4Reliability
If clocks are retuned to synchronize timings across ranks, then clock performance is improved, but device complexity increases
Solution Approach 1:
Clock retuning circuitry implements feedback mechanisms to detect and correct timing variations across different ranks. By monitoring clock signal characteristics and adjusting retuning parameters, the system achieves synchronized timing while keeping the complexity manageable through automated control.
Solution Approach 2:
The patent adjusts clock signal parameters (such as frequency or phase) through retuning circuitry to compensate for variations introduced by different TSV path lengths and loading conditions. This parameter optimization improves synchronization while maintaining a systematic approach to complexity management.
Data Source
AI summary
A memory device includes a first memory chip having first circuits configured to use a clock to perform memory operations and a first transmitter configured to transmit the clock. The memory device also includes a first local interconnect configured to receive the clock from the transmitter and a second memory chip that includes second circuits to use the clock to perform memory operations, a first receiver configured to receive the clock from the first local interconnect, and a second transmitter configured to transmit the clock. The memory device also includes a second local interconnect configured to receive the clock from the second transmitter and a third memory chip located in a stack above the second memory chip. The third memory chip includes third circuits configured to use the clock to perform memory operations, and a second receiver configured to receive the clock from the second local interconnect.