3D Memory Device Staircase Structure for Density Scaling
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling due to limitations in feature size and fabrication costs, leading to density constraints, which 3D memory architecture aims to address by increasing cell density and decoupling peripheral and memory array device processing.
Innovation Solution
A 3D memory device is designed with a substrate, peripheral device, memory stack, and memory strings that extend vertically, featuring a staircase structure of conductor/dielectric layer pairs, interconnect layers, and via contacts to enhance cell density and performance, allowing for separate fabrication of peripheral and memory array devices without thermal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology and fabrication process, then memory density is improved, but feature sizes approach a lower limit and fabrication becomes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture by stacking multiple memory layers vertically. This dimensional change allows continued increase in memory density without further reducing lateral feature sizes, thereby avoiding the fabrication challenges and costs associated with extreme miniaturization of planar cells
2Quantity of substance
If planar memory cells are scaled down further, then memory density is improved, but fabrication costs increase
Solution Approach 1:
By stacking memory layers in the vertical dimension rather than continuing to shrink lateral dimensions, the patent achieves higher memory density using fabrication processes that operate at larger, more cost-effective feature sizes. The 3D stacking approach leverages existing process technologies while avoiding the exponentially increasing costs associated with further planar scaling
3Quantity of substance
If 3D memory architecture is implemented to address density limitation, then memory density is improved, but device complexity increases due to multiple interconnect layers and via contacts
Solution Approach 1:
The patent divides the 3D memory structure into discrete, modular components including multiple memory layers, interconnect layers, and via contact structures. Each layer and component can be independently fabricated and assembled, allowing the complex 3D structure to be built systematically from simpler building blocks, thereby managing device complexity through modular segmentation
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings. Each of the memory strings extends vertically through the memory stack and includes a drain select gate and a source select gate above the drain select gate. Edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the substrate are staggered laterally toward the memory strings.