Solid-State Devices TRIZ Cases

A display panel uses a buffer layer between the encapsulant and first bedding metal to improve laser sintering fusion.

A double-faced display panel uses a reflection unit between sub-units to redirect emitted light back into the active layers.

A switching element uses a lower barrier electrode with distinct density layers to enhance adhesive strength and prevent heat transfer.

Merged gates reduce cell size while maintaining junction breakdown voltage without extra masking steps.

Shield electrodes isolate gate terminals in nitride semiconductor structures, eliminating parasitic capacitance that causes unstable switching and false firing.

A flexible organic electroluminescence display device incorporates a laser-removable release layer to separate the laminate structure from a support substrate.

Segmented inclined walls in the lens recess optimize reflection angles, resolving low light intensity issues in decorative lighting applications.

Insulating and conductive guard dams isolate pixel areas from logic heat, preventing dark current defects.

Variable thickness geometry protects fragile TFT traces from fracture while enabling an ultra-thin borderless device profile.

Organic EL display panel arranges same-color unit pixels adjacently to reduce color mixture during inkjet deposition.

Photolithography patterns a photosensitive layer to define pixels, resolving mask size constraints that limit pixel density below 800 ppi.

Segmented LED packaging reduces optical distance from 8 mm to 2 mm, resolving incomplete light mixing caused by shortened device dimensions.

A hollow pillar of crystalline silicon serves as a bit line and transistor channel within reversible resistivity memory structures.

Resonant magnetic fields synchronize with free layer precession in orthogonal spin transfer MRAM, enabling deterministic switching at lower currents.

Redundant ReRAM devices compensate for stuck states while high-impedance connections prevent unintended state changes from particle strikes.

Vertical stacking of memory strings over peripheral devices resolves fabrication cost trade-offs by decoupling array processing from substrate constraints.

Segmenting deep trenches eliminates loading effects to ensure uniform depth and minimize defects that cause dark current.

Reduced top electrode contact area enables efficient heating while simplifying fabrication process complexity.

A six-transistor two-magnet MRAM cell uses parallel N-type and P-type transistors to form bi-directional transmission gates for write operations.

Selective insulation reduces leakage current while maintaining charge retention and writing efficiency.

A multi-layer bottom anti-reflective coating stack reduces substrate reflectivity to improve thin film resistor dimension matching.

Epitaxial growth on a signal line grid fabricates micro LEDs in place, eliminating transfer misalignment and defects.

A multilayer dielectric film with a tetragonal crystalline structure resolves leakage current and electrode oxidation issues in DRAM capacitors.

A foldable OLED display uses a protruding bending portion to distribute stress across flexible segments.

Per-pixel calibration corrects energy scale offsets and non-linear responses to resolve dual isotope imaging overlap.

A flip-chip light emitting diode uses an undoped semiconductor layer to improve structural strength and production yields.

Stepped pixel electrodes adjust external light reflection directions uniformly across sub-pixels, resolving color separation issues in pentile arrangements.

An anti-oxidation layer protects vertical non-volatile memory gate electrodes from oxidation, maintaining reliability and operational speeds.

Adhesive layers with matched thermal expansion coefficients compensate for stress between flexible substrates and rigid inorganic barriers.

Partition walls define internal regions for color control layers to prevent color mixing and simplify fabrication.

A wedge-shaped light guide plate with stepped LED mounting holes maintains consistent brightness across the display surface.

An image transport layer merges separated pixel images across gaps, eliminating distortion on curved surfaces.

Undercut retaining walls prevent cutting cracks from reaching display regions, reducing frame sizes without compromising panel quality.

Gap portions between floating gates suppress capacitive coupling and threshold voltage variations while preventing water entry into insulation films.

Replacing the glass substrate with a plastic film reduces panel thickness while maintaining cell-assembly accuracy for reliable AMOLED displays.

Applying underfill on dicing tape fills narrow gaps between fine pitch solder bumps, resolving complex topology constraints during wafer-level singulation.

Bonding small light-emitting substrates to a large carrier enables large-substrate equipment use, resolving throughput and cost bottlenecks.

Tuning pick-off mechanism gain suppresses vibration sensitivity and bias errors in MEMS sensors.

Laminated metal PCB layers dissipate heat while maintaining flat mounting surfaces and device compatibility.

A recessed conductor layer connects the shared cathode electrode to an auxiliary contact, enabling stable power distribution across pixels.

Curved interfaces between transparent and reflecting layers control radiant angles for spotlights without a substrate.

Dielectric spacers guide selective epitaxial growth of silicon carbon in trenches to form self-aligned source regions.

Protruding floating gates increase gate coupling ratio and lower operating voltage without adding fabrication complexity.

FinFETs with asymmetrical silicide structures lower parasitic capacitance between the gate and contacts, improving read-write stability in memory devices.

Oxidized substrate metal films enable direct bonding of light emitting elements while maintaining electrical insulation between wiring and the substrate.

An optical sensor taps photo currents from visible and infrared light at separate pn junctions.

An electrical connector joins LED strings while providing physical support between components.

An array substrate shifts shielding to common electrodes outside gate lines and expands aperture ratio where Black Matrix blocks light.

Vertical memory structures use anti-diffusion films on etched conductive surfaces to preserve impurity levels and improve erase speed.

Dual-layer partition walls with graded refractive indices guide light to filter units, reducing optical crosstalk and improving signal strength.