Self-Aligned Source for Split-Gate Non-Volatile Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile flash memory cell technologies face challenges in scaling down memory cell size due to alignment issues between control gate lines and source lines, leading to increased spacing that can result in leakage and the need for optical proximity correction (OPC) to manage critical dimensions.
Innovation Solution
The formation of source regions using dielectric spacers and selective epitaxial growth of silicon carbon (SiC) in trenches within the silicon substrate, allowing for reduced critical dimensions and self-aligned source lines without the need for OPC, thereby controlling the CG-to-SL spacing and minimizing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ion implantation is used to form source regions, then source regions can be formed between gate stacks, but alignment issues between control gate lines and source lines lead to increased spacing requirements that prevent further scaling
Solution Approach 1:
Dielectric spacers are formed on the sidewalls of control gate lines before source line formation. This preliminary structuring establishes precise spatial references that guide subsequent source region formation, ensuring accurate alignment between control gates and source lines without requiring large spacing margins
Solution Approach 2:
Dielectric spacers act as intermediary structures between control gate lines and source lines. These spacers provide a physical reference framework that mediates the alignment relationship, allowing source regions to be precisely positioned relative to control gates through the spacer structure rather than direct alignment
2Reliability
If larger spacing is maintained between control gate lines and source lines to avoid leakage, then alignment tolerance is improved, but memory cell size cannot be reduced
Solution Approach 1:
Dielectric spacers are formed in advance on control gate sidewalls to establish precise alignment references before source line formation. This preliminary structuring enables tight spacing while maintaining leakage prevention through accurate positioning rather than relying on large spacing margins
Solution Approach 2:
The dielectric spacer structure provides self-alignment functionality, where the spacer geometry itself defines the precise location for source region formation. This self-service alignment mechanism ensures consistent spacing and prevents leakage without requiring additional alignment tolerance
3Manufacturing precision
If optical proximity correction is applied to manage critical dimensions, then patterning precision is improved, but process complexity increases
Solution Approach 1:
Dielectric spacers serve as intermediary reference structures that simplify the patterning process. Instead of relying on complex OPC to define source line positions, the spacer structures provide inherent geometric references that guide source region formation with simpler, more direct patterning steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller memory cell sizes with improved control over critical dimensions, reducing the risk of leakage and eliminating the requirement for optical proximity correction, thus facilitating better scaling and alignment in memory cell arrays.
Implementation Method 1
selective epitaxial growth of silicon carbon (SiC) in trenches within the silicon substrate
Data Source
Figure 1
Figure 2A~2B
Figure 3A
AI summary
A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.