Anti-oxidation Layer for Vertical Non-volatile Memory Gate Electrodes
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Solution Overview
Problem
Non-volatile memory devices with vertical structures face challenges in maintaining the reliability of gate electrodes due to oxidation, which affects their performance and integration capabilities.
Innovation Solution
Incorporating an anti-oxidation layer with a dielectric material different from the high-k layer, disposed between the blocking layer and the gate electrodes, to protect them from oxidation, and using a manufacturing method that alternately stacks insulating and conductive layers with precise deposition processes to form the gate dielectric layers and channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate electrodes are exposed during manufacturing processes, then deposition and formation of gate dielectric layers can be performed, but the gate electrodes undergo oxidation which deteriorates their electrical properties and reliability
Solution Approach 1:
A dummy gate electrode structure is introduced as an intermediary element that performs the protective function. The dummy gate electrode is formed over the actual gate electrode during deposition processes, preventing direct oxidation of the gate electrode while allowing deposition equipment access. After deposition of gate dielectric layers, the dummy gate electrode is removed, having served its protective purpose throughout the manufacturing sequence.
Solution Approach 2:
The dummy gate electrode is formed in advance before the actual deposition processes begin. This preliminary structure is prepared specifically to protect the gate electrode during subsequent manufacturing steps. By establishing this protective layer beforehand, the gate electrode is shielded from oxidation during the deposition of gate dielectric layers without requiring process interruptions or modifications to the deposition sequence.
2Ease of manufacture
If conventional planar transistor structure is used, then manufacturing is simpler, but integration density and capacity are limited
Solution Approach 1:
The transistor structure transitions from a conventional planar two-dimensional layout to a three-dimensional vertical architecture. The channel extends vertically through multiple layers rather than horizontally in a single plane, enabling increased storage capacity and integration density within the same footprint. This dimensional transition allows stacking of multiple memory cells vertically, dramatically improving productivity and storage capacity without sacrificing ease of manufacturing the basic structure.
3Reliability
If anti-oxidation layer is added to protect gate electrodes, then reliability improves, but device structure and manufacturing complexity increase
Solution Approach 1:
The protective anti-oxidation function is merged with the existing dummy gate electrode structure rather than being implemented as a separate additional layer. The dummy gate electrode serves dual purposes: it acts as a placeholder for the actual gate electrode during deposition processes and simultaneously functions as the anti-oxidation protective layer. This merging eliminates the need for separate anti-oxidation layers, reducing overall device complexity while maintaining reliability benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The anti-oxidation layer effectively prevents gate electrode oxidation, enhancing the reliability and operational characteristics of non-volatile memory devices, particularly in vertical structures, by maintaining uniform thickness and preventing unintentional oxide film formation, thus improving energy band adjustments and operational speeds.
Implementation Method 1
a gate dielectric layer including a tunneling layer, an electric charge storage layer, and a blocking layer
Implementation Method 2
a blocking layer including a high-k layer and a low-k layer
Data Source
AI summary
There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.