Thin Film Resistor Dimension Matching via Multi-Layer BARC
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Solution Overview
Problem
Conventional patterning techniques for forming matched thin film resistors (TFRs) in semiconductor ICs face challenges in reducing TFR mismatch due to high reflectivity during the photolithography process, leading to significant deviations in resistor size and functionality accuracy.
Innovation Solution
A multi-layer bottom anti-reflective coating (BARC) stack is used for patterning, comprising a dielectric layer, a carbon underlayer, and a silicon hard mask layer, which reduces substrate reflectivity and improves TFR dimension matching by enabling precise etching of TFR patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning techniques are used for forming matched TFRs, then the photolithography process can be performed with standard equipment, but high substrate reflectivity causes significant deviations in resistor size and mismatch
Solution Approach 1:
The patent introduces an intermediary multi-layer BARC stack structure between the substrate and the photoresist layer. This intermediate structure acts as a mediator to reduce substrate reflectivity during photolithography, thereby improving TFR dimension matching without requiring changes to the fundamental photolithography process or equipment.
Solution Approach 2:
The patent employs a composite multi-layer BARC stack comprising multiple materials with different optical and etching properties. Each layer in the stack is designed to address specific issues: the first BARC layer reduces reflectivity, the second BARC layer provides additional anti-reflective properties, and the etch stop layer controls etching depth. This composite approach enables simultaneous optimization of multiple parameters.
2Manufacturing precision
If a multi-layer BARC stack is used to reduce substrate reflectivity, then TFR dimension matching is improved, but the patterning process complexity increases
Solution Approach 1:
The patent segments the anti-reflective coating into multiple distinct layers, each performing a specific function. This segmentation allows for optimized performance of each layer while maintaining overall process compatibility. The segmented structure enables independent optimization of reflectivity reduction and etching control without requiring complete process redesign.
Solution Approach 2:
The patent utilizes parameter changes in the BARC stack structure, specifically controlling the thickness of each layer (first BARC layer: 50-200 nm, second BARC layer: 50-200 nm, etch stop layer: 10-50 nm) and their material composition, to achieve optimal reflectivity reduction and etching control. These parameter adjustments enable precision control of TFR dimensions while maintaining process feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer BARC stack process enhances TFR resistance matching, improving the accuracy and predictability of IC performance by reducing line edge roughness and critical dimension uniformity, thereby ensuring better functionality of analog and mixed-signal ICs.
Implementation Method 1
A multi-layer bottom anti-reflective coating (BARC) stack is used for patterning, comprising a dielectric layer, a carbon underlayer, and a silicon hard mask layer, which reduces substrate reflectivity
Implementation Method 2
Masked etching of the hard mask layer transfers a pattern of a patterned photoresist (PR) layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern
Data Source
AI summary
A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.