Crystalline Silicon Bit Line for Reversible Resistivity Memory

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Solution Overview

Problem

Semiconductor memory devices face challenges such as increased variability in memory cell I-V characteristics and leakage currents due to process, voltage, and temperature variations, particularly as process geometries shrink, affecting the reliability and efficiency of non-volatile memory devices.

Innovation Solution

The use of a reversible resistivity memory structure with a crystalline silicon bit line, where a hollow pillar of crystalline silicon is embedded within a hollow pillar of reversible resistivity material, acting as a channel and bit line, reduces leakage currents and enhances electron mobility by minimizing grain boundaries and defects, thereby improving memory cell performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If process geometries are shrunk to reduce cost per bit, then storage density is improved, but leakage currents increase and variability in memory cell I-V characteristics worsens

Engineering Contradiction:
Improvestorage densityVSAvoidmemory cell I-V characteristics variability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent changes the material parameter from amorphous silicon to crystalline silicon, which fundamentally alters the electrical characteristics by reducing leakage currents and minimizing variability in I-V characteristics. This material parameter change enables continued scaling while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention uses a composite structure combining crystalline silicon channel with reversible resistivity material, creating a hybrid memory cell that leverages the low-defect crystalline silicon for reliable current conduction while using the reversible resistivity material for non-volatile storage functionality.

Inventive Principle:
Principle #40Composite materials

2Quantity of substance

If process geometries are shrunk to reduce cost per bit, then storage density is improved, but leakage currents increase

Engineering Contradiction:
Improvestorage densityVSAvoidleakage currents
Core Design Contradiction:
Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

The patent changes the material parameter from amorphous silicon to crystalline silicon, which fundamentally alters the electrical characteristics by reducing leakage currents and minimizing variability in I-V characteristics. This material parameter change enables continued scaling while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If amorphous silicon bit line is used, then manufacturing is easier, but electron mobility is lower and leakage currents are higher

Engineering Contradiction:
Improvebit line fabricationVSAvoidelectron mobility
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the material parameter from amorphous silicon to crystalline silicon, which fundamentally alters the electrical characteristics by reducing leakage currents and minimizing variability in I-V characteristics. This material parameter change enables continued scaling while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces leakage currents and increases electron mobility, leading to improved memory cell current and reliability, allowing for more efficient and scalable non-volatile memory devices.

Implementation Method 1

enhances electron mobility by minimizing grain boundaries and defects

Methodology Applied
Scientific EffectElectron mobility: Conduction (electrical)

Data Source

PatentUS9685484B1Reversible resistivity memory with crystalline silicon bit line
Publication Date: 2017.06.20 SANDISK TECHNOLOGIES LLC
  • US9685484B1 patent drawing
  • US9685484B1 patent drawing
  • US9685484B1 patent drawing

AI summary

Technology is described for reversible resistivity memory having a crystalline silicon bit line. In one aspect, a memory structure comprises a hollow pillar of crystalline silicon inside of reversible resistivity material. The crystalline silicon may serve as a bit line. The memory structure may further comprise conductive material that forms word lines coupled to the outer surface of the reversible resistivity material. A memory cell comprises a portion of the reversible resistivity material between the crystalline silicon and one of the word lines. In one aspect, the hollow pillar of crystalline silicon surrounds a gate oxide, which surrounds a conductive transistor gate. Thus, the hollow pillar of crystalline silicon may function as a channel of a transistor. In one aspect, the crystalline silicon has predominantly a (100) orientation with respect to an inner surface of the reversible resistivity material. In one aspect, the crystalline silicon is a single crystal.