Wafer-Level Underfill via Dicing Tape for IC Singulation

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Solution Overview

Problem

The challenge in fabricating integrated circuit systems lies in achieving reliable under-fill processes, particularly in complex topologies with fine pitch solder bumps and narrow gaps between stacked components, which are difficult to fill effectively, and the need for methods compatible with temporary bonding/debonding, wafer-level under-fill, and IC chip singulation.

Innovation Solution

The method involves fabricating integrated circuits on a semiconductor substrate with spaced solder bumps, applying a dicing tape with an under-fill material, laminating the substrate to the tape, and then dicing to singulate individual ICs, which are subsequently attached to another substrate with the under-fill material filling spaces between solder bumps, allowing for reliable attachment and protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional under-fill methods are used, then the under-fill material can be applied, but it is difficult to properly fill the space between die and substrate due to complex topologies, fine pitch solder bumps, and narrow gaps

Engineering Contradiction:
Improveunder-fill application precisionVSAvoidcomplex topology
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The under-fill material is applied to the dicing tape before the wafer is diced into individual chips. This preliminary application allows the under-fill to be distributed across the entire wafer surface in advance, avoiding the difficulty of applying it later through narrow gaps between already-bonded components. The material is positioned and partially cured before the final assembly step.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The under-fill application is moved from the vertical dimension (applying through narrow gaps between die and substrate) to the horizontal dimension (applying across the wafer surface on the dicing tape). This dimensional shift allows access to all areas including fine pitch regions without being constrained by the narrow vertical gap between stacked components.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If wafer-level under-fill is implemented, then efficient singulation is achieved, but the process must be compatible with temporary bonding and debonding

Engineering Contradiction:
Improvesingulation efficiencyVSAvoidbonding process compatibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The dicing tape serves as an intermediary substrate that temporarily holds the wafer during the under-fill application process. The tape provides a stable platform for applying and distributing the under-fill material across the wafer surface, while also facilitating easy debonding after the under-fill is cured. This intermediary approach enables wafer-level processing without compromising compatibility with temporary bonding requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The process utilizes controlled temperature and pressure parameters during lamination and curing to achieve proper bonding strength at different stages. The bonding strength is adjusted by controlling the cure state of the under-fill material - initially soft for conformal filling, then progressively stronger during curing, finally achieving full strength for permanent attachment. This parameter control enables compatibility with temporary bonding and debonding requirements.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the under-fill material is applied before dicing, then it fills spaces between solder bumps effectively, but the lamination process must ensure proper alignment and adhesion

Engineering Contradiction:
Improveunder-fill reliabilityVSAvoidlamination complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The under-fill application is merged with the dicing tape lamination process. Instead of applying under-fill separately after dicing, the material is applied to the tape in advance, and the lamination step simultaneously achieves both tape attachment and under-fill positioning. This merging of operations simplifies the overall manufacturing process while ensuring reliable under-fill placement.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The under-fill material provides self-alignment through its viscous flow characteristics during lamination. As the wafer is pressed against the tape with the under-fill in between, the material automatically conforms to the topography and fills gaps between solder bumps without requiring precise manual alignment. The material's flow properties enable it to self-position correctly during the pressing operation.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures reliable under-fill and efficient singulation of ICs, providing a strong mechanical and electrical connection while sealing out contaminants, and is compatible with advanced technologies and temporary bonding processes.

Implementation Method 1

heated to cause the plurality of back side solder bumps to flow and to adhere to metallic pads on the second substrate

Methodology Applied
Scientific EffectSoldering: Soldering

Implementation Method 2

the under-fill material filling spaces between the back side solder bumps

Methodology Applied
Scientific EffectCapillary action: Capillary Action

Implementation Method 3

The carrier wafer is removed and the semiconductor substrate and the layer of under-fill material are diced

Methodology Applied
Scientific EffectDebonding:

Data Source

PatentUS8409927B1Methods for fabricating integrated circuit systems including high reliability die under-fill
Publication Date: 2013.04.02 GLOBALFOUNDRIES US INC
  • US8409927B1 patent drawing
  • US8409927B1 patent drawing
  • US8409927B1 patent drawing

AI summary

A method is provided for fabricating an integrated circuit system that includes fabricating a plurality of integrated circuits in and on a semiconductor substrate. Spaced apart solder bumps are attached to the plurality of integrated circuits, the solder bumps in electrical contact to components of the integrated circuits. A dicing tape having a layer of under-fill material thereon is provided and the semiconductor substrate is laminated to the dicing tape with the layer of under-fill material filling spaces between the solder bumps. The semiconductor substrate and layer of under-fill material are diced to singulate individual ones of the plurality of integrated circuits, and one of the individual ones of the plurality of integrated circuits is attached to a second substrate such as another integrated circuit chip or printed circuit board.