FinFET Asymmetrical Silicide Structures for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional finFET arrangements face challenges due to increased complexity of transistor contacts, leading to parasitic capacitance issues that degrade alternating current performance.
Innovation Solution
The finFET arrangement incorporates asymmetrical silicide structures with adjusted aspect ratios to reduce parasitic capacitance by varying the area and distance of silicide layers relative to the gate, thereby improving AC performance in memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional finFET arrangements use symmetrical silicide structures, then manufacturing is simpler, but parasitic capacitance increases degrading AC performance
Solution Approach 1:
The patent applies asymmetry by configuring different silicide structures on the source and drain sides of the gate. Specifically, a first silicide layer is formed on the source side with different dimensions than a second silicide layer on the drain side. This asymmetrical configuration reduces parasitic capacitance between the gate and silicide structures, thereby improving AC performance while accepting increased manufacturing complexity.
Solution Approach 2:
The patent implements local quality by optimizing silicide structure parameters in different locations. The source-side silicide has specific width and length dimensions, while the drain-side silicide has different dimensions. This localized optimization allows each region to be tuned for its specific electrical requirements, reducing overall parasitic capacitance while maintaining manufacturability through standardized processes.
Data Source
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AI summary
A fin Field Effect Transistor (finFET) arrangement according to the invention can includes a source region and a drain region of the finFET, as well as a gate of the finFET crossing over a fin of the finFET between the source and drain regions. First and second silicide layers are formed on the source and drain regions respectively. The first and second silicide layers include respective first and second surfaces that face the gate crossing over the fin, where the first and second surfaces have different sizes.