P-Channel MTP Memory Cell Structure for Reduced Size
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Solution Overview
Problem
Existing multi-time programmable (MTP) memory cells require additional processing steps and result in large cell sizes due to design rule requirements, necessitating the development of a simpler and cost-free MTP structure using standard CMOS technology.
Innovation Solution
The integration of a p-channel MTP memory cell with a semiconductor substrate, including an n-well and a p-well, a p-channel transistor, and a p-channel capacitor, where the capacitor gate is coupled to the transistor gate, allowing for reduced cell size and improved breakdown voltage without additional masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional masking steps are used to achieve high junction breakdown voltage, then breakdown voltage is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the capacitor and transistor structures by sharing the p-well region and using a common gate electrode structure. The capacitor gate and transistor gate are formed as a single integrated structure, eliminating the need for separate masking steps for each component while maintaining the required breakdown voltage characteristics.
Solution Approach 2:
The p-well structure serves multiple functions simultaneously: it acts as the capacitor substrate, provides the transistor channel region, and establishes the breakdown voltage characteristics. This multi-functional design eliminates the need for additional processing steps dedicated to separate voltage control structures.
2Manufacturing precision
If design rule requirements are followed, then manufacturing precision is maintained, but cell size increases
Solution Approach 1:
The capacitor and transistor are merged into a single integrated structure where the capacitor gate and transistor gate share the same physical space and formation process. This merging allows the cell to meet design rule requirements while achieving a compact footprint that would be impossible with separate structures.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional integration to achieve compact cell size. By forming the capacitor and transistor in overlapping regions and using multiple layers, the design maintains planar design rule compliance while reducing the overall cell area through vertical space utilization.
Data Source
AI summary
Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an embodiment, an MTP memory cell includes a semiconductor substrate, a p-well formed in the semiconductor substrate, and an n-well formed in the semiconductor substrate and isolated from the p-well. The MTP memory cell further includes a p-channel transistor disposed over the n-well and including a transistor gate. Also, the MTP memory cell includes a p-channel capacitor disposed over the p-well and including a capacitor gate. The capacitor gate is coupled to the transistor gate.