Floating Gate Protrusion for Non-Volatile Memory GCR

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Solution Overview

Problem

As the integration of non-volatile memory devices increases, it becomes difficult to enhance the gate coupling ratio (GCR) between the floating gate and the control gate, limiting the reduction of operating voltage and device efficiency due to constraints in increasing the overlapped area between these components in conventional stacked gate structures.

Innovation Solution

The implementation of a non-volatile memory design where the floating gate has a protruding portion fully covered and surrounded by the control gate in various directions, increasing the overlapped area and thus the GCR, while also reducing interference between adjacent floating gates, achieved through a specific fabricating method involving patterning and etching processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the integration level of non-volatile memory devices is increased, then device density is improved, but the overlapped area between floating gate and control gate becomes difficult to increase, causing gate coupling ratio to deteriorate

Engineering Contradiction:
Improvedevice integration levelVSAvoidgate coupling ratio
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The floating gate is designed with a protruding portion that extends in the first direction (perpendicular to substrate), adding a vertical dimension to the overlap area. This three-dimensional configuration increases the effective overlapped area between floating gate and control gate without consuming additional planar space, thereby maintaining high gate coupling ratio while achieving high device integration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The protruding portion of the floating gate is fully covered and surrounded by the control gate in all directions (first direction, second direction, and directions at angles between them). This nested configuration maximizes the overlapping area while minimizing the footprint, enabling both high integration and high gate coupling ratio.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the overlapped area between floating gate and control gate is increased to enhance gate coupling ratio, then device performance is improved, but device complexity increases due to additional patterning steps

Engineering Contradiction:
Improvegate coupling ratioVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The same mask is used for both forming the conductive layer (which becomes the floating gate with protruding portion) and forming the control gate. This merging of patterning steps into a single operation achieves the complex three-dimensional overlapping structure without requiring additional fabrication steps, thereby maintaining high gate coupling ratio while minimizing process complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If the protruding portion of floating gate is surrounded by control gate to reduce interference between adjacent floating gates, then device reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveinterference reduction between floating gatesVSAvoidpatterning precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

By using a single mask to define both the protruding portion of the floating gate and the control gate, the relative positioning and surrounding relationship are automatically established with high precision. This merged patterning approach eliminates alignment errors between separate steps, achieving the required manufacturing precision while maintaining the surrounding configuration that reduces interference between adjacent floating gates.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8741754B2Fabricating method of non-volatile memory
Publication Date: 2014.06.03 POWERCHIP SEMICON MFG CORP
  • US8741754B2 patent drawing
  • US8741754B2 patent drawing
  • US8741754B2 patent drawing

AI summary

A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction.