ReRAM Memory Cell Redundancy and Radiation Tolerance
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Solution Overview
Problem
Resistive random-access memory (ReRAM) devices used in configuration memories for user-programmable integrated circuits can be faulty, stuck in one state, or enter an intermediate state, requiring redundancy to ensure proper operation, which complicates their design and functionality.
Innovation Solution
A nonvolatile memory cell configuration that includes a ReRAM device with a p-channel transistor and an n-channel transistor, along with an inverter, connected between voltage supply nodes and an output node, allowing for single ReRAM device operation with redundancy options through multiple ReRAM devices that are individually selectable, and incorporating high-impedance connections to enhance radiation tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If ReRAM devices are used in configuration memories, then nonvolatile storage is achieved, but device reliability deteriorates due to faults and stuck states
Solution Approach 1:
The patent implements redundancy at the bit level by duplicating the ReRAM device and associated circuitry (transistors and inverters) within each configuration memory cell. This redundant structure is prepared in advance to compensate for potential device failures, stuck states, or intermediate states that may occur during operation, ensuring continuous reliable functionality without requiring complete cell replacement.
2Reliability
If redundancy is provided to ensure proper operation, then reliability is improved, but device complexity increases due to multiple selectable ReRAM devices
Solution Approach 1:
The patent segments the redundancy implementation into modular units at the bit level, where each configuration memory cell contains its own redundant ReRAM device and associated circuitry. This segmentation allows independence of redundant elements, enabling selective activation of backup components only when needed, thereby managing complexity through organized modularity rather than monolithic redundancy structures.
Solution Approach 2:
The patent implements dynamic selection between primary and redundant ReRAM devices through control logic that can switch between devices based on operational status. This dynamic approach allows the system to adaptively activate redundancy only when faults are detected, rather than requiring all redundant components to be permanently active, thus reducing effective complexity during normal operation while maintaining reliability protection.
3Object-affected harmful factors
If high-impedance connections are used, then radiation tolerance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes high-impedance connections as a parameter change in the electrical characteristics of the configuration memory cell interconnects. By increasing the impedance of these connections, the patent reduces the coupling of radiation-induced charges between adjacent cells and reduces susceptibility to single-event upsets, thereby improving radiation tolerance while managing the associated manufacturing precision requirements through design optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures reliable operation by reducing the need for dual ReRAM devices, providing redundancy without doubling the cell count, and enhancing radiation tolerance by managing voltage biases effectively, thus preventing unintended state changes due to particle strikes.
Implementation Method 1
causing metal ions from the ion source conductive electrode to migrate into the solid electrolyte layer and form a conductive path between the two conductive electrodes
Implementation Method 2
ReRAM devices employ a solid electrolyte material disposed between two conductive electrodes
Implementation Method 3
at least one p-channel transistor connected between the second electrode of the resistive random access memory device and the output node, at least one n-channel transistor connected between the output node and the second voltage supply node
Implementation Method 4
an inverter connected between the output node and a gate of the at least one n-channel transistor
Data Source
AI summary
A nonvolatile memory cell includes a first voltage supply node, a second voltage supply node, an output node, a resistive random access memory device having a first electrode and a second electrode, the first electrode connected to the first voltage supply node, at least one p-channel transistor connected between the second electrode of the resistive random access memory device and the output node, at least one n-channel transistor connected between the output node and the second voltage supply node, and an inverter connected between the output node and a gate of the at least one n-channel transistor.