MRAM 6T2M Cell Bi-Directional Write Path
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Solution Overview
Problem
Traditional spin torque transfer magnetoresistive random-access memory (STT MRAM) experiences reduced writing speed and increased switching voltage when writing to the anti-parallel state due to source degeneration, which affects the efficiency of data storage.
Innovation Solution
The implementation of a 6T2M structure in the MRAM, where each N-type transistor is coupled in parallel with a corresponding P-type transistor, allowing for bi-directional current during write operations and preventing source degeneration by ensuring that the write-in current is provided by either N-type or P-type transistors depending on the state, thereby maintaining high writing speed and reducing switching voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the non-volatile storage unit is located on the source end of the N-type transistor during anti-parallel state writing, then the write operation can be performed, but source degeneration occurs which reduces the write-in current and writing speed
Solution Approach 1:
The unit cell is divided into two separate write paths: one for parallel state writing using N-type transistors, and another for anti-parallel state writing using P-type transistors. This segmentation allows each transistor type to operate in its optimal configuration without source degeneration, resolving the contradiction between write operation capability and writing speed.
Solution Approach 2:
Instead of using only N-type transistors for both write operations, the invention inverts the approach by using P-type transistors for anti-parallel state writing. This inversion eliminates the source degeneration problem that occurs when N-type transistors are used in that configuration, thereby maintaining high writing speed while enabling the write operation.
2Ease of operation
If the non-volatile storage unit is located on the source end of the N-type transistor during anti-parallel state writing, then the write operation can be performed, but the write-in current is reduced due to source degeneration requiring higher switching voltage
Solution Approach 1:
The write operation is segmented into two independent paths: N-type transistors handle parallel state writes, and P-type transistors handle anti-parallel state writes. This segmentation ensures that each path uses the appropriate transistor type to avoid source degeneration, thereby maintaining low switching voltage requirements while enabling full write operation capability.
Solution Approach 2:
The invention inverts the conventional approach by assigning P-type transistors to anti-parallel state writing instead of N-type transistors. This inversion eliminates source degeneration and its associated voltage penalty, allowing the write operation to be performed with reduced switching voltage.
3Device complexity
If a 3T2M structure is used, then the device complexity is low, but source degeneration occurs during anti-parallel state writing
Solution Approach 1:
The unit cell is segmented into six transistors (3N-type and 3P-type) with dedicated write paths for parallel and anti-parallel states. This segmentation increases device complexity slightly but completely eliminates source degeneration by ensuring each write operation uses the appropriate transistor type in its optimal configuration.
Solution Approach 2:
The invention introduces P-type transistors to invert the conventional N-type-only approach. This inversion adds three transistors per unit cell but eliminates source degeneration entirely, as P-type transistors are used for anti-parallel state writing where they do not suffer from source degeneration effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances writing speed and reduces the required switching voltage, ensuring efficient data storage operations without source degeneration, particularly during the transition to the anti-parallel state.
Implementation Method 1
A spin torque transfer (STT) MRAM utilizes a magnetic tunnel junction (MTJ) as the memory storage. The magnetization direction of one ferromagnetic layer is fixed while that of the other ferromagnetic layer can be altered by a switching voltage. Magnetization of the free layer is used to store the data and can be switched by spin-polarized electrons.
Implementation Method 2
magnetoresistive random-access memory (MRAM) stores data in magnetic domains
Data Source
AI summary
In an MRAM, each unit cell includes two non-volatile storage units, three N-type transistors and three P-type transistors. Each N-type transistor is coupled in parallel with a corresponding P-type transistor for forming a transmission gate which provides bi-directional current, thereby preventing source degeneration.