3D Memory Staircase Layout to Prevent Word Line Opens
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Solution Overview
Problem
Manufacturing 3D semiconductor memory devices with a complex circuit structure is challenging due to defects such as word line opens and pattern failures, making it difficult to achieve high memory capacity with reduced defects.
Innovation Solution
A 3D semiconductor device with a staircase configuration of stack units, where conductive films and dielectric films are alternately stacked, and conductive pillars are used to form thin film transistors, allowing for a more efficient manufacturing process with reduced defects by using specific etching techniques to form word lines and bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a 3D architecture is used to increase memory capacity, then memory capacity is improved, but manufacturing complexity and defect rate increase
Solution Approach 1:
The patent transitions from a conventional 2D memory array to a 3D architecture where word lines extend vertically through multiple stacked memory layers. This dimensional change allows memory capacity to be increased by utilizing the third dimension (stack height) rather than only expanding the planar area, thereby achieving higher density without proportionally increasing manufacturing complexity
Solution Approach 2:
The 3D memory structure is divided into multiple stacked memory layers, each with its own set of bit lines and select transistors. This segmentation allows the complex 3D structure to be manufactured through repeated application of standardized process modules, reducing overall manufacturing complexity by breaking down the monolithic 3D structure into manageable repeating units
2Quantity of substance
If a 3D architecture is used to increase memory capacity, then memory capacity is improved, but defect rate increases
Solution Approach 1:
The word lines are formed to extend continuously through all memory layers in advance, before the bit lines and contact structures are created. This preliminary formation of vertical word line pathways ensures proper electrical connectivity is established early in the manufacturing process, preventing word line open defects that would otherwise occur with conventional sequential fabrication approaches
Solution Approach 2:
The patent introduces intermediate contact structures and isolation layers that mediate between the vertical word lines and the horizontal bit lines. These intermediary elements facilitate proper electrical connection while preventing short circuits and pattern failures, thereby reducing the defect rate in the 3D architecture
3Ease of manufacture
If conventional manufacturing processes are used for 3D devices, then manufacturing simplicity is maintained, but manufacturing yield decreases
Solution Approach 1:
The manufacturing process employs periodic repetition of standardized process modules to form multiple stacked memory layers. Each module includes sequential steps for forming memory cells, bit lines, and select transistors that are repeated N times to create the 3D stack. This periodic application of proven 2D fabrication processes enables scaling to 3D while maintaining manufacturing simplicity and achieving high yield through process standardization
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, first and second stack units disposed over the semiconductor substrate, and a feature disposed between the first and second stack units. Each of the first and second stack units includes at least one stack that includes a conductive film and a dielectric film stacked on each other. The feature includes a plurality of repeating units and a plurality of separators disposed to alternate with the repeating units. Each of the repeating units includes an inner portion including a pair of conductive pillars, and an outer portion including a memory film and a channel film. A method for manufacturing the semiconductor device is also disclosed.