3D Memory Cell Step-Edge Layout for Lower Word Line Interference
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Solution Overview
Problem
The integration density of two-dimensional semiconductor memory devices is limited due to the high cost and complexity of pattern refinement tools, prompting the need for three-dimensional semiconductor memory devices with vertically stacked memory cells to enhance integration and reduce interference among word lines.
Innovation Solution
A semiconductor memory device with a vertically stacked memory cell array, featuring a bit line, a capacitor, an active layer, a word line, and a back gate, where the edges of the word line and back gate form a step shape to prevent interference, allowing for increased integration density and reduced parasite capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use conventional planar structures, then manufacturing processes are simpler, but integration density is limited due to area constraints and word line interference
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked along the vertical direction (first direction) with bit lines extending in the second direction and word lines in the third direction, enabling higher integration density by utilizing the third dimension for cell arrangement
Solution Approach 2:
The memory cell is divided into distinct functional components arranged in specific spatial relationships: bit lines extending in the second direction, word lines in the third direction, and active layers positioned at intersections, allowing independent optimization of each component while achieving high integration
2Quantity of substance
If word lines are closely spaced to increase integration density, then more memory cells fit in the same area, but interference among adjacent word lines increases
Solution Approach 1:
Word lines are arranged in the third direction rather than being parallel in the same plane, allowing closely spaced word lines to be physically separated in three-dimensional space. This vertical stacking approach reduces capacitive coupling and interference between adjacent word lines while maintaining high density
Solution Approach 2:
Insulating layers are introduced between adjacent word lines and between word lines and bit lines to electrically isolate conductors that are in close proximity. These intermediary insulating structures prevent direct interference while allowing the conductors to maintain compact spacing for high integration
3Area of stationary object
If memory cells are vertically stacked to increase integration density, then area occupancy is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Multiple memory cells are combined into a single vertically stacked structure sharing common bit lines and word lines. This merging approach reduces the total area occupancy while the shared conductor structures help establish precise alignment relationships between stacked cells through common reference planes
Data Source
AI summary
The present invention provides a highly integrated memory cell and a semiconductor memory device including the same. According to the present invention, a semiconductor memory device comprises: a memory cell array in which a plurality of memory cells is vertically stacked to a substrate, wherein each of the memory cells includes: a bit line vertically oriented to the substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; and a word line and a back gate facing each other with the active layer interposed therebetween, and wherein an edge of the word line and an edge of the back gate have a step shape along a stacking direction of the memory cells.