3D Memory Bonding Structure With Stopper Layer Thickness Control
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity while maintaining electrical properties and reliability, particularly in three-dimensional memory cell configurations.
Innovation Solution
A semiconductor device design featuring a first semiconductor structure with a substrate, circuit devices, and interconnection structures, and a second semiconductor structure with vertically stacked gate electrodes, channel structures, and stopper layers, where the thickness of the first stopper layer is thinner than the second stopper layer, enhancing electrical connections and manufacturing ease.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed three-dimensionally to increase data storage capacity, then storage capacity is improved, but manufacturing complexity and reliability are worsened
Solution Approach 1:
The device is divided into two separate semiconductor structures (first and second structures) that are bonded together. The first structure contains circuit devices and the second structure contains memory cells with vertically stacked gate electrodes. This segmentation allows each structure to be optimized independently for its specific function while achieving high storage capacity through 3D stacking, thereby maintaining reliability despite increased complexity.
Solution Approach 2:
Multiple gate electrodes are stacked vertically within the second semiconductor structure, with channel structures penetrating through them. This nested arrangement of gate electrodes and channel structures enables high-density 3D memory cell configuration, increasing storage capacity while maintaining manageable manufacturing processes through standardized stacking techniques.
2Quantity of substance
If memory cells are disposed three-dimensionally to increase data storage capacity, then storage capacity is improved, but manufacturing complexity is worsened
Solution Approach 1:
The complex 3D memory structure is segmented into two separate semiconductor structures that can be manufactured independently using conventional planar processes, then bonded together. This reduces the complexity of individual manufacturing steps while achieving the overall 3D configuration needed for high storage capacity.
Solution Approach 2:
The memory cells achieve three-dimensional configuration by stacking gate electrodes vertically in the second semiconductor structure, transitioning from 2D planar arrangement to 3D stacked arrangement. This dimensional change increases storage capacity per unit area while maintaining manufacturing feasibility through standardized stacking processes.
3Reliability
If stopper layer thickness is reduced to improve electrical connections, then electrical properties are improved, but manufacturing precision requirements are worsened
Solution Approach 1:
Different stopper layer thicknesses are used in different regions: the first stopper layer has a first thickness optimized for electrical connection quality, while the second stopper layer has a second thickness optimized for manufacturing precision and structural support. This local differentiation allows each layer to fulfill its specific function optimally without compromising overall device performance.
Data Source
AI summary
A semiconductor device includes a first semiconductor structure including circuit devices on a first substrate, a lower interconnection structure connected to the circuit devices, and a lower bonding structure connected to the lower interconnection structure; and a second semiconductor structure including a second substrate on the first semiconductor structure, a stopper layer in contact with a lower surface of the second substrate, gate electrodes stacked and spaced apart from each other in a vertical direction, channel structures penetrating through the gate electrodes, and each including a channel layer, an upper interconnection structure below the gate electrodes, a peripheral contact plug spaced apart from the second substrate, and an upper bonding structure bonded to the lower bonding structure, wherein the channel structures penetrate at least a portion of the stopper layer, and wherein the peripheral contact plug penetrates at least a portion of the stopper layer.