3D Semiconductor Memory Devices Using Direct Strapping Line Connections
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited by the area occupied by a unit memory cell and the expense of fine pattern forming technology, hindering increased integration and cost-effectiveness.
Innovation Solution
The development of three-dimensional semiconductor memory devices with elongate gate stacks, insulation regions, conductive plugs, and strapping lines, where the insulation regions have varying widths and are connected to a common source region, allowing for increased integration and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor memory devices are used, then the manufacturing process is relatively simple, but the integration degree is limited by the area occupied by a unit memory cell and fine pattern forming technology costs
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Multiple memory cell layers are stacked vertically with gate stacks extending in the vertical direction, allowing integration scaling without increasing planar footprint. This dimensional transition enables higher integration density while maintaining manufacturing feasibility through sequential layer formation processes.
2Manufacturing precision
If three-dimensional semiconductor memory devices with multiple layers are implemented, then integration degree increases, but manufacturing process complexity and equipment costs increase
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete memory cell layers stacked vertically. Each layer contains memory cells formed between adjacent gate stacks, with insulation regions separating different layers. This segmentation allows independent formation and patterning of each layer, simplifying the manufacturing process compared to attempting to form all structures simultaneously, while achieving high integration through vertical stacking.
Data Source
AI summary
Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.