3D Memory Stress Compensation via Oxide and Conductive Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for manufacturing three-dimensional memory structures, such as vertical NAND strings, face challenges in achieving efficient stress management and structural integrity, which affects the convex vertical profile and overall performance of the memory devices.
Innovation Solution
A method involving the formation of alternating stacks of insulating and sacrificial material layers, followed by semiconductor material deposition and conversion into dielectric oxide layers, with additional stress application through subsequent layer stacks, to create a monolithic three-dimensional memory array with controlled stress profiles and enhanced structural bending.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternating stacks of insulating and sacrificial material layers are formed with subsequent dielectric oxide layers, then stress management and structural integrity are improved, but device complexity and manufacturing process steps increase
Solution Approach 1:
The structure is divided into alternating stacks of insulating and sacrificial material layers, with additional dielectric oxide layers inserted at specific positions. This segmentation allows independent control of stress profiles in different regions, enabling precise stress management while maintaining structural integrity throughout the three-dimensional memory device.
Solution Approach 2:
Dielectric oxide layers are formed on the sacrificial material layers before the sacrificial material is removed. This preliminary action ensures that the stress compensation structure is already in place to support the subsequent structural changes and prevent deformation when the sacrificial material is eliminated.
2Shape
If dielectric oxide layers are formed on sacrificial material layers, then stress compensation and convex vertical profile are enhanced, but manufacturing time and process duration increase
Solution Approach 1:
The formation of dielectric oxide layers on sacrificial material layers is combined with the existing alternating stack formation process. By integrating these steps into the overall manufacturing sequence rather than adding separate operations, the convex vertical profile is achieved without proportionally increasing total manufacturing time.
Solution Approach 2:
The stress profile parameters are controlled by adjusting the thickness and positioning of dielectric oxide layers relative to the sacrificial material layers. By optimizing these parameters, the convex vertical profile is achieved with minimal additional material and process steps, reducing the impact on manufacturing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of monolithic three-dimensional NAND string memory devices with improved stress management and structural integrity, leading to enhanced performance and reliability of the memory structures.
Implementation Method 1
The dielectric oxide layer 24 applies a second type stress, which is compressive stress, to the substrate 10
Implementation Method 2
semiconductor material deposition and conversion into dielectric oxide layers
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A first stack of alternating layers including first insulating layers and first sacrificial material layers is formed on a substrate. Dielectric oxide layers applying compressive stress are formed on the top surface of the first stack and on the bottom surface of the substrate. A second stack of alternating layers including second insulating layers and second sacrificial material layers is formed over the top dielectric oxide layer. After formation of lateral recesses by removal of the first and second sacrificial material layers, a bottom dielectric oxide layer is removed. A conductive material applying a tensile stress is deposited into the backside recesses to form electrically conductive layers. The compressive stress applied by the top dielectric oxide layer partially cancels the tensile stress applied by the electrically conductive layers, and reduces the curvature of the substrate that has a concave bottom surface.