3D Memory Conductive Strip Isolation for Read Disturbance
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Solution Overview
Problem
As 3-dimensional memory devices increase in storage density and integration, disturbance between elements becomes more severe, affecting operational efficiency.
Innovation Solution
Incorporation of a lower isolation structure that separates conductive layers into electrically isolated strips, allowing independent control of memory strings and reducing capacitance in channel layers during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage density and integration of 3-dimensional memory devices are increased, then storage capacity is improved, but disturbance between elements becomes more severe
Solution Approach 1:
The conductive layers are divided into multiple conductive strips by the lower isolation structure, which physically segments the memory device into isolated regions. This segmentation reduces capacitive coupling and interference between adjacent memory strings, thereby decreasing disturbance between elements while maintaining high storage density.
Solution Approach 2:
The lower isolation structure is positioned specifically in the lower portion of the stacked structure to provide localized electrical isolation where it is most needed. This local quality approach allows the conductive layers to remain continuous in upper portions where isolation is less critical, optimizing both performance and manufacturing complexity.
2Object-affected harmful factors
If lower isolation structure is introduced to separate conductive layers, then read disturbance is decreased, but device complexity increases
Solution Approach 1:
The lower isolation structure segments the conductive layers into electrically isolated strips, creating distinct regions that prevent signal interference during read operations. This segmentation reduces read disturbance by isolating capacitive coupling between adjacent memory strings while maintaining a relatively simple overall device architecture.
Solution Approach 2:
The lower isolation structure acts as an intermediary element between adjacent conductive layers, providing electrical isolation without requiring complex restructuring of the entire memory device. This intermediary approach effectively reduces read disturbance while adding minimal structural complexity.
Data Source
AI summary
A memory device and a method for manufacturing the same are provided. The memory device includes a stacked structure, a lower isolation structure in the stacked structure and two memory strings in the stacked structure. The stacked structure includes conductive layers. The lower isolation structure has an upper surface in a lower portion of the stacked structure. The lower isolation structure separates at least one conductive layer of the conductive layers into a first conductive strip and a second conductive strip. The first conductive strip and the second conductive strip are electrically isolated from each other. Two memory strings are electrically connected to the first conductive strip and the second conductive strip respectively.