3D Semiconductor Memory Sub-Cell Terraced Structures
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Solution Overview
Problem
Current three-dimensional semiconductor memory devices face challenges in achieving high integration density and reliability while maintaining operational speed due to limitations in pattern formation techniques and equipment costs.
Innovation Solution
A three-dimensional semiconductor memory device design featuring a substrate with sub-cell regions and strapping regions, where sub-gates are sequentially stacked with lateral extensions, and vertical-type channel patterns penetrate these sub-gates, along with interconnections and bitlines for enhanced electrical connectivity and data storage layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional structures are adopted to increase integration density, then the number of memory cells per unit area increases, but reliability and operational speed deteriorate
Solution Approach 1:
The memory device is divided into multiple sub-cell regions (first sub-cell region, second sub-cell region, etc.) separated by strapping regions. Each sub-cell region contains its own vertical channel patterns and sub-gates, creating modular segments that can be independently controlled and tested, thereby improving reliability while maintaining high integration density through the three-dimensional stacked architecture
Solution Approach 2:
Strapping regions are introduced as intermediary zones between sub-cell regions, containing strapping lines that provide electrical connections and voltage supply to the sub-gates. These intermediary structures act as buffers and connection highways, enabling reliable signal and power distribution across the three-dimensional structure without compromising operational speed
2Quantity of substance
If three-dimensional structures are adopted to increase integration density, then the number of memory cells per unit area increases, but operational speed deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked structures, with multiple sub-gates stacked in the vertical dimension and vertical channel patterns extending through the stack. This dimensional change allows significantly higher integration density while the strapping regions provide dedicated power and signal pathways that maintain fast operational speeds by reducing resistance and improving electrical connectivity
Solution Approach 2:
Strapping lines in the strapping regions serve as intermediary conductors that directly connect to the extensions of sub-gates, providing low-resistance electrical pathways for voltage supply and signal transmission. This intermediary connection system ensures that despite the three-dimensional complexity, the operational speed is maintained through efficient electrical connectivity
3Ease of manufacture
If conventional pattern formation techniques are used, then manufacturing processes remain simple, but integration density is limited and equipment costs increase
Solution Approach 1:
The manufacturing process is segmented into modular steps that form different components (channel patterns, sub-gates, strapping regions, interconnections) separately and then assemble them into the final three-dimensional structure. This segmentation allows each component to be formed using conventional, well-established fabrication techniques, maintaining process simplicity while achieving high integration density through the modular three-dimensional architecture
Solution Approach 2:
The patent employs a nested structure where multiple sub-gates are stacked vertically within each sub-cell region, with vertical channel patterns penetrating through the stacked sub-gates. This nesting approach allows multiple memory cells to be stacked in the vertical dimension using sequential deposition and patterning steps, achieving high integration density while relying on conventional manufacturing processes rather than requiring expensive specialized equipment
Data Source
AI summary
Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.