3D Memory Test Pattern Integration for Reliable Electrical Measurements
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Solution Overview
Problem
The reliability of data obtained through test patterns in three-dimensional semiconductor memory devices is low due to independent formation processes from cell array structures, leading to inconsistent electrical characteristics.
Innovation Solution
A semiconductor memory device is designed with a multifunctional stack including interlayer insulating and conductive layers, a liner insulating and semiconductor layer, and electrodes, integrated with a three-dimensional memory cell array structure to enhance the reliability of test patterns and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a test pattern is formed through an independent process from the cell array structure, then the test pattern can be formed separately, but the reliability of data obtained through the test pattern is low
Solution Approach 1:
The patent combines the test pattern formation process with the cell array structure formation process into a single integrated process. The test pattern is formed within the same groove structure that forms the memory cell array, using the same liner insulating layer, liner semiconductor layer, and electrode formation steps. This merging ensures that the test pattern experiences identical processing conditions as the cell array, thereby improving measurement reliability while maintaining ease of manufacture through process integration.
2Adaptability or versatility
If the test pattern is formed independently from the cell array structure, then manufacturing flexibility is improved, but measurement consistency deteriorates
Solution Approach 1:
The patent creates a universal groove structure that serves multiple functions: it forms both the memory cell array and the test pattern. The same liner insulating layer, liner semiconductor layer, and electrode formation process is used for both purposes. This multi-functional approach allows manufacturing flexibility to be maintained while ensuring measurement consistency, as both structures experience identical processing conditions and material deposition.
Data Source
AI summary
There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a doped semiconductor layer including an upper surface facing a first direction, a multifunctional stack including a plurality of interlayer insulating layers and a plurality of conductive layers stacked alternately with each other in the first direction above the doped semiconductor layer, the multifunctional stack including a groove, a liner insulating layer on a bottom surface of the groove, a liner semiconductor layer on the liner insulating layer, and a first electrode and a second electrode spaced apart from each other in the groove and extending in the first direction from the liner semiconductor layer.