3D Memory Control Logic Stacks With Vertical TFT Subdecks
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Solution Overview
Problem
Semiconductor device designers face challenges in increasing the packing density and reducing the size of memory devices due to complications in electrical connections and interconnect structures in three-dimensional memory arrays, which hinder performance and fabrication cost reductions.
Innovation Solution
A semiconductor device with a multi-deck structure featuring a base control logic structure and a stack structure, where each deck includes a memory element level, an access device level, and a thin film transistor (TFT) control logic level, with vertically displaced subdeck structures of NMOS and PMOS transistors, reducing the need for interconnects and allowing for independent control logic operations within each deck.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells and decks in a 3D memory array is increased, then storage density is improved, but the complexity of routing and interconnect structures increases, creating sizing and spacing complications
Solution Approach 1:
The patent transitions from two-dimensional planar control logic to three-dimensional vertically-stacked control logic structures. Multiple decks of control logic devices are stacked vertically above the memory array, with each deck serving specific memory cells. This vertical stacking reduces the lateral footprint and minimizes interconnect complexity by bringing control logic closer to the memory cells in the vertical dimension.
Solution Approach 2:
The control logic is divided into multiple discrete decks, where each deck contains specific control logic devices that can be independently configured and connected to particular memory cells. This segmentation allows for modular design, reducing the overall complexity by breaking down the monolithic interconnect structure into smaller, manageable segments.
2Adaptability or versatility
If the quantity of control logic devices is increased to support more memory cells, then functionality is improved, but the size of the memory device increases and fabrication costs rise
Solution Approach 1:
Control logic devices are arranged in vertical stacks extending upward from the memory array, utilizing the vertical dimension to accommodate multiple decks of control logic without proportionally increasing the lateral device footprint. This enables enhanced functionality while maintaining compact device dimensions.
Solution Approach 2:
Multiple decks of control logic devices are configured to serve different memory cells within the same lateral footprint. Each deck can be independently activated to control specific memory cells, allowing a single vertical column to perform multiple control functions for different memory locations, thereby reducing the overall number of control logic devices needed.
3Reliability
If traditional routing structures are used to connect memory cells to control logic, then electrical connection is achieved, but spacing requirements increase and packing density is reduced
Solution Approach 1:
Electrical connections are established primarily in the vertical dimension through vertically-extending interconnect structures that connect memory cells directly to control logic devices in stacked decks above them. This vertical connection approach eliminates the need for extensive lateral routing, reducing spacing requirements and increasing packing density while maintaining reliable electrical connections.
Data Source
AI summary
A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.