Transistor TRIZ Cases

Perovskite epitaxial oxide plugs near source and drain regions restore channel strain lost in FinFET processing, improving carrier mobility.

A silicon oxynitride protection layer with annealed nitrogen reduction prevents source/drain oxidation and improves contact formation reproducibility.

Segmented double-height cell regions use active, dummy fin, and gate patterns to pack standard and custom cells more efficiently.

Normally-on anti-series switches discharge substrate voltage in both directions, keeping it near 0 V and improving bidirectional switching.

Series-stacked short-channel MOSFETs emulate long-channel behavior to reduce current mismatch and raise output resistance in deep-submicron analog ICs.

Varying Fe concentration and layer thickness across stacked memory cells offsets annealing differences to keep coercive force and magnetoresistance uniform.

A buried-channel JFET-GAA gate structure cuts dielectric trap noise while preserving high-speed semiconductor performance.

Selective etching and dielectric fill create buried isolation beneath GAA FET channels to suppress sub-channel leakage in scaled devices.

Sharp top corners and oblique sidewalls in the floating gate improve flash erase ability, speed control, and cell pattern density.

A top-gate planar oxide semiconductor transistor cuts parasitic capacitance and resistance to raise on-current while keeping low off-current.

A metal oxide mask and sacrificial-layer flow keep GAA nanosheet gate heights uniform across different channel widths, protecting yield.

A dual-gate oxide TFT linked to a transparent OLED electrode cuts photomasks while improving on-current and threshold stability.

A combined source-drain contact is cut and insulated to prevent shorts while enabling tighter NFET-PFET spacing in GAA nanosheet layouts.

Single-layer gate, source, and drain electrodes improve alignment and cut fabrication defects in light-emitting display structures.

Forming gate cuts before epitaxial source/drain growth uses sacrificial trench fill and a dielectric liner to avoid etch damage.

A variable-width fin and uneven gate dielectric help one multi-gate transistor support low- and high-voltage SoC operation with lower leakage.

Thin recessed fin protrusions keep transistor fin widths controlled, easing etching while reducing short-channel effects and improving switch sensitivity.

Parallel transistor-capacitor sub-bit units with binary-weighted capacitance store 2^N values, boosting memory density and computing speed.

Separated through via structures with varied size tune resistance and protect integrated circuit layer performance in stacked semiconductor wiring.

Varying spacer thickness and conductive feature width lets one substrate tune parasitic resistance and capacitance across mixed semiconductor devices.

Reflowing a semiconductor layer creates smooth inner-spacer sidewalls in GAA transistors, improving source/drain epitaxy and reducing interface defects.

Reflected light and color filters let a sensor substrate detect product placement and removal without RFID tags or weight sensors.

An MBE-grown silicon barrier between the FinFET channel and gate dielectric suppresses Ge diffusion, lowers GeOx, and improves BTI stability.

Selective etch stop deposition on a protection cap enables self-aligned via formation, reducing over-etch, material loss, and RC delay.

Dummy mandrels inserted between layout blocks enable denser self-aligned patterning, improving fin uniformity and shape accuracy.

A higher-withstand current detection structure and sensing resistor keep reverse-bias surges from damaging the monitor before the main device.

A selective dielectric barrier enables maskless NFET and PFET silicide formation, cutting process complexity while improving resistivity.

Alternating-etch templates shape semiconductor fins and self-align gate endcaps to cut resistance, capacitance, leakage, and layout penalty.

A tailored etching composition uses inhibitors and surfactant chemistry to remove silicon selectively while protecting SiGe, metals, SiN, and low-k layers.

Regular nanowire and pad pitches align chip blocks to simplify nanowire FET manufacturing and reduce process-induced variation.

A vertical transistor memory layout uses the bitline as source or drain to raise cell density while limiting defect spread into the channel.

Air gaps around FinFET vias and fins lower ILD dielectric constant, cutting parasitic capacitance with minimal process cost.

Oxidized fin structures extend channel length in HV/LV integration, cutting leakage while improving breakdown voltage control.

Selective etching and metal deposition create an extended gate electrode that lowers resistance while preserving reliable semiconductor scaling.

A wraparound conductive layer contacts epitaxial source or drain sidewalls to expand contact area and lower ohmic resistance.

Sub-source lines and select transistors isolate a flash memory subrow, enabling byte erase without disturbing other cells.

A bottom dielectric under source/drain epitaxy blocks substrate leakage, reduces DIBL, and helps lower parasitic capacitance.

Silicon germanium mandrels enable double channel FinFET regions, boosting current capacity while improving epitaxial uniformity and reducing defects.

An active gate cut and recess isolates work function metal patterning at tight N/P boundaries while preserving gate continuity and threshold voltage.

Multiple control terminals tune floating-gate voltage and channel conductance to store multi-state data and implement low-power neuromorphic neurons.

Hydrogen-formed high-concentration regions control depletion spread near guard rings to reduce breakdown voltage fluctuation in semiconductor substrates.

Selective sidewall barriers and surface passivation cut corrosion without raising device resistance in scaled interconnect filling.

Dual dopant implantation in a display thin-film transistor cuts hysteresis and afterimage while simplifying crystallization and doping.

Adjacent dummy fins are replaced with dielectric fins to balance iso/dense etch loading and keep FinFET fin widths uniform at smaller nodes.

A P-N junction body structure enables back bias in vertical FETs to steepen subthreshold slope, cut leakage current, and improve on/off ratio.

A dielectric-filled notch in the VFET source/drain edge cuts parasitic capacitance and isolation leakage while supporting dense vertical scaling.

Vertical NMOS and PMOS TFT subdecks bring control logic into each 3D memory deck, cutting interconnect complexity and boosting density.

A comb-shaped bit line with substrate-facing pins simplifies DRAM interconnect fabrication while supporting higher cell density and performance.

Preforming a metal-filled power rail opening and exposing it after thinning improves backside alignment accuracy and power support.

Shared main electrode regions in adjacent amplification transistors cut pixel readout noise without enlarging circuit layout or sensitivity variation.