Transistor TRIZ Cases

Perovskite epitaxial oxide plugs near source and drain regions restore channel strain lost in FinFET processing, improving carrier mobility.

A silicon oxynitride protection layer with annealed nitrogen reduction prevents source/drain oxidation and improves contact formation reproducibility.

Segmented double-height cell regions use active, dummy fin, and gate patterns to pack standard and custom cells more efficiently.

Normally-on anti-series switches discharge substrate voltage in both directions, keeping it near 0 V and improving bidirectional switching.

Series-stacked short-channel MOSFETs emulate long-channel behavior to reduce current mismatch and raise output resistance in deep-submicron analog ICs.

Varying Fe concentration and layer thickness across stacked memory cells offsets annealing differences to keep coercive force and magnetoresistance uniform.

A buried-channel JFET-GAA gate structure cuts dielectric trap noise while preserving high-speed semiconductor performance.

Selective etching and dielectric fill create buried isolation beneath GAA FET channels to suppress sub-channel leakage in scaled devices.

Sharp top corners and oblique sidewalls in the floating gate improve flash erase ability, speed control, and cell pattern density.

A top-gate planar oxide semiconductor transistor cuts parasitic capacitance and resistance to raise on-current while keeping low off-current.

A metal oxide mask and sacrificial-layer flow keep GAA nanosheet gate heights uniform across different channel widths, protecting yield.

A dual-gate oxide TFT linked to a transparent OLED electrode cuts photomasks while improving on-current and threshold stability.

A combined source-drain contact is cut and insulated to prevent shorts while enabling tighter NFET-PFET spacing in GAA nanosheet layouts.

Single-layer gate, source, and drain electrodes improve alignment and cut fabrication defects in light-emitting display structures.

Forming gate cuts before epitaxial source/drain growth uses sacrificial trench fill and a dielectric liner to avoid etch damage.

A variable-width fin and uneven gate dielectric help one multi-gate transistor support low- and high-voltage SoC operation with lower leakage.

Thin recessed fin protrusions keep transistor fin widths controlled, easing etching while reducing short-channel effects and improving switch sensitivity.

Parallel transistor-capacitor sub-bit units with binary-weighted capacitance store 2^N values, boosting memory density and computing speed.

Separated through via structures with varied size tune resistance and protect integrated circuit layer performance in stacked semiconductor wiring.

Varying spacer thickness and conductive feature width lets one substrate tune parasitic resistance and capacitance across mixed semiconductor devices.

Reflowing a semiconductor layer creates smooth inner-spacer sidewalls in GAA transistors, improving source/drain epitaxy and reducing interface defects.

Reflected light and color filters let a sensor substrate detect product placement and removal without RFID tags or weight sensors.

An MBE-grown silicon barrier between the FinFET channel and gate dielectric suppresses Ge diffusion, lowers GeOx, and improves BTI stability.

Selective etch stop deposition on a protection cap enables self-aligned via formation, reducing over-etch, material loss, and RC delay.

Dummy mandrels inserted between layout blocks enable denser self-aligned patterning, improving fin uniformity and shape accuracy.

A higher-withstand current detection structure and sensing resistor keep reverse-bias surges from damaging the monitor before the main device.

A selective dielectric barrier enables maskless NFET and PFET silicide formation, cutting process complexity while improving resistivity.

Alternating-etch templates shape semiconductor fins and self-align gate endcaps to cut resistance, capacitance, leakage, and layout penalty.

A tailored etching composition uses inhibitors and surfactant chemistry to remove silicon selectively while protecting SiGe, metals, SiN, and low-k layers.

Regular nanowire and pad pitches align chip blocks to simplify nanowire FET manufacturing and reduce process-induced variation.

A vertical transistor memory layout uses the bitline as source or drain to raise cell density while limiting defect spread into the channel.

Air gaps around FinFET vias and fins lower ILD dielectric constant, cutting parasitic capacitance with minimal process cost.

Oxidized fin structures extend channel length in HV/LV integration, cutting leakage while improving breakdown voltage control.

Selective etching and metal deposition create an extended gate electrode that lowers resistance while preserving reliable semiconductor scaling.

A wraparound conductive layer contacts epitaxial source or drain sidewalls to expand contact area and lower ohmic resistance.

Sub-source lines and select transistors isolate a flash memory subrow, enabling byte erase without disturbing other cells.

A bottom dielectric under source/drain epitaxy blocks substrate leakage, reduces DIBL, and helps lower parasitic capacitance.

Silicon germanium mandrels enable double channel FinFET regions, boosting current capacity while improving epitaxial uniformity and reducing defects.

An active gate cut and recess isolates work function metal patterning at tight N/P boundaries while preserving gate continuity and threshold voltage.

Multiple control terminals tune floating-gate voltage and channel conductance to store multi-state data and implement low-power neuromorphic neurons.

Hydrogen-formed high-concentration regions control depletion spread near guard rings to reduce breakdown voltage fluctuation in semiconductor substrates.

Selective sidewall barriers and surface passivation cut corrosion without raising device resistance in scaled interconnect filling.

Dual dopant implantation in a display thin-film transistor cuts hysteresis and afterimage while simplifying crystallization and doping.

Adjacent dummy fins are replaced with dielectric fins to balance iso/dense etch loading and keep FinFET fin widths uniform at smaller nodes.

A P-N junction body structure enables back bias in vertical FETs to steepen subthreshold slope, cut leakage current, and improve on/off ratio.

A dielectric-filled notch in the VFET source/drain edge cuts parasitic capacitance and isolation leakage while supporting dense vertical scaling.

Vertical NMOS and PMOS TFT subdecks bring control logic into each 3D memory deck, cutting interconnect complexity and boosting density.

A comb-shaped bit line with substrate-facing pins simplifies DRAM interconnect fabrication while supporting higher cell density and performance.

Preforming a metal-filled power rail opening and exposing it after thinning improves backside alignment accuracy and power support.

Shared main electrode regions in adjacent amplification transistors cut pixel readout noise without enlarging circuit layout or sensitivity variation.

Ink composition undergoes spontaneous combustion to form dense indium-zinc-oxide thin films, eliminating high heat treatment requirements.

A drain electrode completely covers an active layer end to shield the semiconductor from manufacturing damage.

Segmented gate conductors with an undoped intermediate section block dopant diffusion to preserve threshold voltage accuracy during device scaling.

Stacked imaging devices minimize light leakage into charge detection circuits by positioning photoelectric conversion layers above the readout logic.

A solid-state imaging pixel uses inter-pixel separation units protruding toward the center to form projection portions.

A semiconductor contact plug features a curved lower surface that conforms to source drain regions.

A hybrid-bonded image sensor architecture separates photodiodes and circuitry onto distinct dies to maximize light-sensitive area.

An isolated gate driver adjusts the power device gate voltage slope using a dynamic control unit and insulation part.

A suspended semiconductor layer increases resistance between source and drain electrodes in an array substrate.

A silicon transistor in a cascode configuration conducts sink current to protect gallium nitride devices from overvoltage stress.

Self-aligned SiGe base regions and shared sub-collectors adjust holding voltage while maintaining compact footprint for dual direction ESD events.

Gate insulating film shields oxide semiconductor from hydrofluoric acid, enabling LTPS and TAOS TFTs on one substrate.

Load inductance measurement system detects external load characteristics before power switch activation to enable safe operation.

Inverting the discharge path to the power supply terminal enables overcurrent protection when voltage drops to ground, preventing thermal destruction.

A dual gate oxide semiconductor thin film generates photocarriers via a potential gradient across the active layer.

Shielding regions electrostatically protect the intrinsic base of a silicon carbide bipolar junction transistor.

A contact plug formation process widens upper openings using a mask layer to improve gap filling with conductive materials.

A tensile-stressed layer on a p-type field effect transistor generates compressive stress in the channel to increase hole mobility.

A vertical pin-type capacitor uses a recessed trench structure to increase capacitance density within an image sensor pixel region.

Conductive via structure creates direct leakage path from MIM capacitor top plate to substrate, enabling accurate voltage contrast detection of electric leaks.

A semiconductor device uses a silicon nitride second passivation layer with controlled hydrogen concentration to protect the channel.

Selective reduction of oxide semiconductor resistance enables higher aperture ratios without increasing manufacturing complexity.

Excess nitrate ions in coating solution form dense metal-oxygen-metal bond networks on plastic substrates below 200°C.

Segmented gate spacers with varying dopant concentrations boost drive currents in FinFETs without increasing manufacturing complexity.

A double gate driving transistor uses its top gate electrode to store threshold voltage information via a compensating capacitor.

Dielectric strength control forces voltage breakdown within the semi-insulating region, preventing device destruction during electrical overstress events.

A high voltage lateral double diffused metal oxide semiconductor device uses a heavily doped P+ source region to lower parasitic base resistance.

Patsnap Eureka analyzes a method where fin structures form recesses to guide epitaxial layer growth, preventing isolation overlap and improving layer quality.

Segmented unit transistors stabilize driving transistor characteristics, reducing oxide TFT deviations that degrade display quality.

Bias generation circuit mirrors and amplifies current to set transistor gate states, preventing damage from initial start-up current.

A bipolar junction transistor drive system adjusts base current polarity to manage carrier accumulation.

Roughened back surface electrodes improve adhesion to sealing members, resolving reliability issues in vertical power transistors.

A TiO intermediate layer enables continuous TiN film formation through subsequent nitridation.

Parallel pn and Schottky diodes in freewheeling units generate reverse peak currents that suppress switching oscillations without increasing energy losses.

Silicon nitride dielectric layers maintain capacitor contact area to reduce parasitic capacitance and resistance in dynamic random access memory.

A compound switch configuration reduces power loss by simultaneously shutting off normally-on and normally-off transistors during reverse conduction.

Replacing high-k dielectrics with self-aligned air gaps reduces parasitic capacitance, boosting semiconductor device integration and refresh characteristics.

A wireless chip antenna integrates a metal foil layer with a flexible substrate to create a robust radiating structure.

A vertical junction field-effect transistor uses an all-around gate structure to control current flow in the channel region.

A diode-based temperature sensor estimates junction temperature using differential forward voltage measurements across distinct diode structures.

Dual-layer liner prevents oxidation and charge trapping while enabling void-free gap filling in high aspect ratio FinFET trenches.

A mesh shaped lower electrode expands the dielectric film contact area to increase electrostatic capacitance in semiconductor devices.

Moisture diffuses through the insulating layer during annealing to increase oxide semiconductor conductivity, reducing parasitic resistance between electrodes.

Integrating dummy bit contacts into well contact regions prevents plasma damage without increasing chip area or degrading delay performance.

Dislocation planes in a FinFET structure reduce leakage current by improving gate control over the channel region in deep sub-30nm devices.

Distinct electrode spacing and selective light shielding reduce parasitic capacitance on scanning lines without decreasing the aperture ratio.

Carbon nanotube wires define nano-scaled channels in thin film transistors, avoiding photoresist collapse and residue issues.

Black matrix between substrate and thin film transistor blocks external light, preventing semiconductor layer irradiation to enhance display quality.

A comparator-controlled high-current N-channel FET isolates semiconductor devices from overvoltage by shutting off current flow when the drain voltage exceeds a safe threshold.

A semiconductor memory selection transistor uses nonuniform doping to create distinct threshold voltages across its channel regions.

A temporary metal connection line balances electric potential between conductive patterns to prevent electrostatic discharge during etching.

A bipolar transistor uses a trench collector and epitaxial base to shrink the device footprint.

Applying same-polarity voltages to adjacent pixels with different electrode structures reduces flicker and enhances viewing angle characteristics.

A dynamic field plate bias circuit adjusts transistor breakdown voltage to improve electrostatic discharge protection.

Dummy poly layer patterns on shallow trench isolation form metal-oxide-metal decoupling capacitors to reduce voltage fluctuations without increasing chip area.

Shared well structures merge FinFET and PLVT fabrication, eliminating extra masks while enhancing ideality and reducing leakage current.

A diode chain coupled to a control voltage generator drives a discharger for electrostatic discharge protection.

A base layer connects the MOS gate to the semiconductor substrate for charge dissipation.

A non-volatile programmable memory cell isolates transistors in separate wells to manage programming operations.

Integrates a conductive layer and insulating layer between the thin film transistor and organic light-emitting diode to form an internal storage capacitor.

Stacked conductive layers connect via bridge electrodes to minimize non-display area gaps while equalizing resistance through varied contact hole sizes.

Vertical wiring layers connect bonding pads through a pulling-out region, reducing planar dimension while maintaining terminal density.

Segmented isolation regions eliminate complex charge pumps, reducing manufacturing costs while maintaining reliable voltage levels.

An organic insulating layer with an in-situ silicon oxide surface resists oxygen ion etching to maintain insulation integrity and prevent recess formation.

Alternating thinner and thicker oxide portions near the gate reduce conduction path resistance while maintaining blocking voltage capability.

A semiconducting layer turning portion with asymmetric inner and outer edge curvatures reduces resistance differences in display panel array substrates.

A multiple-finger ESD protection device layout with perpendicular base contacts ensures uniform triggering across all fingers.

A stacked gate structure uses varied oxide thicknesses to pattern polysilicon and composite gates with a single mask.

A high voltage transistor design divides the source region into multiple sections using shallow trench isolation structures to reduce electrical resistance.

A cover layer shields the first contact surface during processing to prevent contamination and ensure reliable ohmic contact formation.

A silicide-blocking layer covers source/drain edges to prevent unwanted metal extension during fabrication.

Sense gate trench extends into main well region to reduce electric field concentration.

Segmented insulating and stress liners optimize operating characteristics for highly integrated fin field effect transistors.

Specific hole transport auxiliary layer compounds lower driving voltage and extend device lifetime by optimizing charge transport efficiency.

Dual-layer dielectric isolation maintains consistent transconductance by using flowable oxide fill and thermal oxide etch resistance.

An indium cerium zinc oxide sputtering target achieves carrier mobility of 12.3 to 46.3 cm2 V−1 s−1 while maintaining device stability.

A metal oxide semiconductor thin film transistor uses an organic gate dielectric layer to enable low temperature fabrication.

Stepped graphene protrusions expand the contact area with a transition metal dichalcogenide, resolving limited junction efficiency in photodetectors.

Shaped diffusion regions in silicon-on-insulator transistors lower on-resistance per unit area for compact radio-frequency switching designs.

A semiconductor device applies well bias voltage through dummy junction areas connected to bias contacts.

Sacrificial lattice layers enable uniform lateral etching between nanoribbons, preventing electrical shorting and reducing parasitic capacitance.

A non-volatile memory control gate uses multilayer conductive patterns with distinct crystallization temperatures to fill field recesses.

A dimmer circuit diverts drive current via a secondary switch to protect the primary MOSFET from damage.

High-temperature silicon doping densifies flowable interlayer dielectric layers to enhance structural integrity and etch resistance.

A hybrid pillar bottom electrode structure protects high aspect ratio electrodes during semiconductor fabrication.

A metal barrier layer protects the active layer during source and drain formation in thin film transistors.

A high voltage driving circuit arrangement uses a protection circuit with current mirrors and a threshold comparator to detect short circuits.

A semiconductor storage device power supply protection circuit manages voltage levels across pads to control transistor states.

Local N-well doping reduces parasitic PNP current gain, mitigating leakage currents in ultra-high voltage semiconductor devices.

Regrown semiconductor layers match gate heights across Si/Ge and Group III-V channels, resolving topography variation during CMP processing.

A polysilicon resistor forms within a shallow trench isolation tank to align with metal gate transistors.

Curved P column patterns balance dopant charges in superjunction MOSFET corners, maintaining uniform electric fields and consistent breakdown voltage.

Canted body contacts with asymmetric polygon shapes reduce on-state resistance by preserving effective channel width while minimizing gate pitch.

Segmented guard rings with nonconducting parts block noise transmission between logic and analog units, ensuring reliable operation.

A single-crystalline organic semiconductor channel layer forms via temperature processing to create uniform crystal orientation.

Self-aligned p-type channel formation reduces depletion width to boost breakdown voltage and lower on-resistance.

CMP separates polysilicon IGFET gates from adjacent semiconductor elements, eliminating extra mask steps.