Floating Gate Geometry for Faster Flash Memory Erase
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Solution Overview
Problem
Current flash memory cells face limitations in erasing ability and speed, which are not adequately addressed by existing technologies.
Innovation Solution
A flash memory cell design featuring a floating gate with two sharp top corners and oblique sidewalls, allowing for improved erasing ability and controlled erasing speed through adjustable sharp top corners and oblique sidewalls, along with the use of blocking structures for self-alignment and flexible gate shapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional floating gate structures are used, then manufacturing is simpler, but erasing ability and speed are insufficient
Solution Approach 1:
The floating gate structure implements local quality by creating sharp top corners and oblique sidewalls in specific regions. The sharp top corners concentrate electric field at localized positions to enhance tunneling efficiency during erasing, while the oblique sidewalls provide controlled field distribution. This localized structural optimization improves erasing ability without requiring complete redesign of the entire memory cell structure.
Solution Approach 2:
The floating gate employs asymmetric geometry with sharp top corners and oblique sidewalls that are not uniformly distributed. This asymmetric structure creates non-uniform electric field distribution during erase operations, concentrating the field where needed to improve erasing speed and ability. The asymmetric design breaks the symmetry of conventional floating gates to achieve superior erase performance.
2Productivity
If floating gate geometry is optimized for erasing, then cell pattern density increases, but manufacturing precision requirements increase
Solution Approach 1:
The method applies preliminary action by forming the floating gate structure with pre-designed sharp corners and oblique sidewalls before subsequent processing steps. The blocking structures are formed first to define the floating gate pattern, ensuring that the critical geometric features are established early in the manufacturing process when alignment and patterning can be optimized for these specific features.
Solution Approach 2:
The floating gate structure exhibits self-service characteristics where the sharp top corners and oblique sidewalls automatically concentrate the electric field during erase operations without requiring additional control mechanisms. The geometric features themselves perform the field concentration function, eliminating the need for complex external control systems or additional processing steps to achieve the desired field distribution.
Data Source
AI summary
A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.